Iota » History » Version 10
steve-m, 02/19/2016 10:49 PM
add link to bottom scan
| 1 | 1 | laforge | This is the Analog Baseband Chip TWL3025 |
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| 2 | 2 | laforge | |
| 3 | 8 | laforge | It's very similar to its predecessors, the TWL3014 and TWL3016 devices. |
| 4 | |||
| 5 | A data sheet for the TWL3014 is available from http://www.52rd.com/bbs/Detail_RD.BBS_8719_68_1_1.html |
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| 6 | but forum registration is required for download. |
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| 7 | |||
| 8 | 7 | laforge | It consists of various functions, including |
| 9 | 10 | steve-m | * ADC and DAC for the GSM baseband signals |
| 10 | * ADC and DAC for the Voice/Audio path |
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| 11 | * DAC for APC (Automatic Power Control) |
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| 12 | * DAC for AFC (Automatic Frequency Control) |
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| 13 | * Battery Charging Controller |
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| 14 | * LDO's (Linear Power Regulators) |
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| 15 | 7 | laforge | |
| 16 | 1 | laforge | The functions of the ABB are controlled by a register set. The register set |
| 17 | 7 | laforge | is available through both USP and BSP. |
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| 20 | 10 | steve-m | h2. External Interfaces == |
| 21 | USP (uController Serial Port) === |
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| 22 | |||
| 23 | 1 | laforge | This is the SPI-like control interface between DBB and the TWL3025 (ABB). |
| 24 | |||
| 25 | [[Image(Iota:twl3025_usp.png)]] |
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| 26 | |||
| 27 | |||
| 28 | 10 | steve-m | h3. TSP (Timee Serial Port) |
| 29 | 1 | laforge | |
| 30 | 10 | steve-m | |
| 31 | It is connected to the TSP controller inside the [[HardwareCalypso]] DBB. |
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| 32 | |||
| 33 | 9 | steve-m | The CLK6.5 Signal makes things a bit more complicated than we would like. The sequence of events is something like: |
| 34 | 10 | steve-m | * CLK_13M is applied continuously to TWL3025 |
| 35 | * nTEN is in default state of high (inactive) |
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| 36 | * internal CLK6.5 is in default state low |
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| 37 | * nTEN is asserted low by TPU, some 0..65ns before CLK_13M rising edge |
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| 38 | * next CLK13M falling edge starts first CLK6.5 rising edge |
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| 39 | * every falling edge of CLK13M toggles CLK6.5 |
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| 40 | * TDR is sampled at every rising edge of CLK6.5 (including the first edge above) |
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| 41 | * 7 bits are transferred during seven rising edges of CLK6.5 |
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| 42 | * TEN stays asserted for 1 CLK13M period after last bit is transferred |
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| 43 | * TEN needs to be released before next CLK13M rising edge to prevent another transfer |
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| 44 | 1 | laforge | |
| 45 | |||
| 46 | 10 | steve-m | h3. BSP (Baseband Serial Port) |
| 47 | 7 | laforge | |
| 48 | 10 | steve-m | |
| 49 | This synchronous serial port is connected to the RIF (Radio [[InterFace]]) of the Calypso DBB. |
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| 50 | |||
| 51 | |||
| 52 | h3. Debug traces |
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| 53 | |||
| 54 | 9 | steve-m | |
| 55 | 1 | laforge | The chip has very tiny debug traces on a small flex-pcb around the 4 sides of the chip. |
| 56 | Which trace goes to which ball can be seen on this scan: http://www.steve-m.de/pictures/iota_bottom.jpg |
