Iota » History » Version 5
laforge, 02/19/2016 10:48 PM
1 | 1 | laforge | This is the Analog Baseband Chip TWL3025 |
---|---|---|---|
2 | 2 | laforge | |
3 | 3 | laforge | == USP == |
4 | |||
5 | This is the SPI-like control interface between DBB and the TWL3025 (ABB). |
||
6 | 5 | laforge | |
7 | 4 | laforge | [[Image(Iota:twl3025_usp.png)]] |
8 | 3 | laforge | |
9 | 2 | laforge | == TSP == |
10 | |||
11 | The CLK6.5 Signal makes things a bit more complicated than we would like. The sequence of events is something like: |
||
12 | * CLK_13M is applied continuously to TSL3025 |
||
13 | * nTEN is in default state of high (inactive) |
||
14 | * internal CLK6.5 is in default state low |
||
15 | * nTEN is asserted low by TPU, some 0..65ns before CLK_13M rising edge |
||
16 | * next CLK13M falling edge starts first CLK6.5 rising edge |
||
17 | * every falling edge of CLK13M toggles CLK6.5 |
||
18 | * TDR is sampled at every rising edge of CLK6.5 (including the first edge above) |
||
19 | * 7 bits are transferred during seven rising edges of CLK6.5 |
||
20 | * TEN stays asserted for 1 CLK13M period after last bit is transferred |
||
21 | * TEN needs to be released before next CLK13M rising edge to prevent another transfer |
||
22 | |||
23 | [[Image(Iota:twl3025_tsp_serial.png)]] |