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UmTRX » History » Version 13

laforge, 02/21/2016 08:52 AM

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{{>toc}}
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h1. Welcome to the [[UmTRX]] project Developer Wiki
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!{width=40%}UmTRX-scheme_simple-cropped-1024w.jpg!
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[[UmTRX]] is a dual-channel wide-band SDR transceiver that is designed to be used with "OpenBTS":http://wush.net/trac/rangepublic and "OsmoBTS":http://openbsc.osmocom.org/trac/wiki/OsmoBTS GSM base stations. Given its SDR architecture [[UmTRX]] can easily be used with many other RF applications, and a combination of FPGA and FPRF (Field-Programmable RF) technology plus the ability to process data on a CPU or a DSP, makes it an extraordinarily flexible platform.
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[[UmTRX]] is connected to a host via gigabit Ethernet. The Fairwaves version of UHD provides FPGA HDL and firmware, along with a host driver.
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Laboratory packages and turnkey solutions are available from "Fairwaves":http://fairwaves.ru/.
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h2. Intro, user info and blog
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For a more detailed introduction, user information (e.g. hardware setup/booting/flashing, software setup) and the project blog, please see "h2. Development
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* [[Architecture"httpumtrxorg]]
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* Design documentation, UHD sources and datasheets etc.
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* Mailing list: "* [[MailingListRules|Mailing list rules"httplistsosmocomorgcgi-binmailmanlistinfoumtrx]]
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* Issue tracker: "(to be migrated to this Trac instance!)
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*** [[ReportingIssues|Guidance on reporting issues"httpscodegooglecompumtrxissueslist]]
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* [[Building_firmware|Building firmware]]
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* [[LMS6002DCalibration|LMS6002D calibration]]
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* [[PowerConsumption|Power consumption]]
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* [[PostProductionTesting|Post-production testing]]
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* Roadmap
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*** [[UmTRX_Roadmap|UmTRX]] 
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*** [[UHD-Fairwaves_Roadmap|UHD-Fairwaves]]
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h2. Licensing
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Altium Designer schematic and board layout files are made available under the Creative Commons Attribution-!ShareAlike 3.0 Unported license.
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FPGA HDL, and firmware and host driver sources are made available under the GPL v3 license.
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h2. Community
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[[UmTRX]] is an Osmocom project and a partner project of "Myriad-RF":http://myriadrf.org/.
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h2. Contributors
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* Alexander Chemeris — project leader
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* Andrey Sviyazov — hardware design
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* Jean-Samuel Najnudel — hardware design and manufacturing
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* Sergey Kostanbaev — FPGA HDL
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* Andrey Sviyazov — initial host-side code
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* Sylvain Munaut — various improvements
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* Eric Wild — host-side code
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* Sergey Kostanbaev — debugging
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* Andrey Bakhmat — logo, diagrams and photos
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* Andrew Karpenkov — FPGA development
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* Andrew Back — community management
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