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Feature #2484

closed

Architecture of USB E1/T1/J1 adapter

Added by laforge over 4 years ago. Updated over 1 year ago.

Status:
Resolved
Priority:
Low
Assignee:
Category:
-
Target version:
-
Start date:
09/02/2017
Due date:
% Done:

100%

Spec Reference:
Tags:
E1

Description

So far we have for many years the Osmo-e1-xcvr board which remains unused. It contains the LIU but no logic that can actually control the LIU and/or process the data.

The interface of the LIU is
  • receive data + clock (output)
  • transmit data + clock (input)
  • SPI for control (SDO,SDI,SCLK,CS) + IRQ
  • LOS (loss of signal) output (can be read via SPI, not required on controller)
Based on what we know about XMOS, this would need:
  • four 1-bit ports for rx/tx+clk per E1 Line
  • three shared 1-bit ports for SPI (shared)
  • part of a multi-bit input port as IRQ input
  • part of a multi-bit output port as CS output

As a result, a XMOS based device for four E1 ports needs 19 1-bit ports plus 2x 4-bit ports. This is possible with a XU[F]216 part in TQFP-128 package.

No I/O voltage translation is required, and plenty of pins remain unused for LEDs or control of a GPS-DO to provide a proper clock reference.

On the USB side, isochronous endpoints should be used for the bitstream. The question in terms of software is how much processing should the XMOS code do, and how much do we perform on the host CPU. Classic E1 interfaces perform functions like
  • frame synchronization
  • (optional) CRC-4
  • timeslot de-multiplex
  • (optional) HDLC inside signaling slots

Related issues

Related to E1/T1 Hardware Interface (including icE1usb) - Feature #3242: develop software for E1 framing / deframing, CRC4, alignment FSMResolvedlaforge05/06/2018

Actions
Related to E1/T1 Hardware Interface (including icE1usb) - Feature #3237: Come up with GPS-DO design for E1 InterfaceRejectedvogelchr05/04/2018

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