Hardware Projects » Misc Hardware Projects

Does it have to be a separate board ?

I would think some simple 0R links to switch between external LVDS lines or the ones generated by the TI LVDS converter would be enough and only have one PCB.
This would also potentially allow to easily monitor the LVDS lines externally by mounting 470R resistors instead of the 0R, then connect the SMA to a scope in 50ohm mode (creating sort of a 1:10 probe).

After creating the footprint for the SN65LVDS180 and placing it close to the SFP, it reveals that this would mean crossed Rx/Tx diff pairs (see images) which is not desirable. Those wires should go straight on top layer into the transceiver. I've committed that xcvr lib anyway, but will continue likely with a pair of SN65LVDS1 and SN65LVDT2.

Huh ... don't you have TX/RX swapped on the SFP there ?!?

RD pins are the SFP receiver pins i.e. they are outputs.

See https://www.embrionix.com/storage/app/media/resources/HOST%20RT-nonnonMSA.gif for instance.

tnt wrote:

Huh ... don't you have TX/RX swapped on the SFP there ?!?

RD pins are the SFP receiver pins i.e. they are outputs.

You are right... sorry for the noise!

Changed this, then Rx and Tx pairs are not crossed anymore but the diff pairs swap P and N. Just tried it with SN65LVDT2 / SN65LVDS1, and no twisting takes place. A 'discrete' solution (separate Rx/Tx ICs) would also give the advantage of easier placing them close to the SMA and hence reducing the single-ended path length.

Attaching two pictures of experiments dony by tnt yesterday

Committed libs for SN65LVDS1 and SN65LVDT2 (single port LVDS tx /rx) and will continue to design with them.

committed a first proposal for an SFP experimenter PCBA.

remarks:

• the width of the differential signal traces and the two single-ended towards the SMA will change until production. The 'edge-coupled coplanar waveguide w/ GND' calculation will change it:
• to achieve reasonable width values but stay with a 2-layer PCB, we might want to take a different FR4 thickness, e.g. 1mm or 0.8mm. Drawback on this is: different types of SMA edge conn are needed for those thin PCBs
• the decoup caps on the driver/receiver might change to 0402 and probably move closer to the respective IC's supply pins
• the selected pinout for driver and receiver in compatible with other manufacturer's types (PI90LVB01 / PI90LV02 , FIN1001/2 ...) I think
• X3 and X5 won't be placed here ('residue' for/from #3313)
• some receivers already integrate the 100R termination while others don't. An R footprint in front of IC3's inputs should be added which can stay unpopulated depending on the receiver type.
• I don't insist on the LDO (TLV1117; loss would be about 1/2W) ;)

13:25 < tnt> Any "real" design using the SFP would be 4 layer, so I guess it's an argument
             to make the experimentation board as close to what a final product would use.

so let's go four-layer. mschramm: please change layer stack-up, add gnd/vcc planes, and adjust trace widths for "usual" four-layer stacking.

A couple of comments :

• Add pin headers for power input/output as well (both before and after the regulator in case tapping the 3.3v can be useful to power something 'else').
• Add leds for TX fault and LOS (with transistor to drive them, not directly from the signal of course)
• Make sure a ground pin is available next to the broken out 'TX_DISABLE' pin. It's internally pulled up and so having a GND next to it would allow to easily use a jumper to force it low and force enable TX.
• Having a couple of GND points to tie scope ground would be neat as well :p

for the record: EAGLE designs are in http://git.osmocom.org/osmo-small-hardware/tree/sfp-breakout

PCB also revised:

• 4 layer stack
• LDO is now a MCP1825
• input protection w/ Schottky series diode and TVS

Suggestions by tnt from #3314#note-12 pending, trying to integrate them today.

just added LOS and TX_FAULT LEDs and more supply pin header as well as a GND pin beside TX_DISABLE - as asked by tnt .

Thanks. I extended the default clearance from 0.15mm (was looking quite small in getbv) to 0.25mm, re-ran the DRC and now ordered 10 boards from Seeed.

As a side note for future projects: Reverse polarity protection with a PMOS is better than diodes, it avoids the voltage drop.

Source to power supply
Drain to circuit
Gate connected to gnd through a pull down resistor.

If power supply is connected backwards, Gate is above the source and the PMOS channel is OFF (and the body diode is reverse biased), so no current will flow.
In normal operation, the channel will be on and so the PMOS will have a low Rds_on and drop very little voltage/power.

For the version with LVDS transceiver I find myself often wanting to connect pin headers to the in/out ... so I'm wondering if adding some right next (or even over) the SMA pads would be a good idea. I mean the idea here is to have 'slowish' single ended data, so SMA is a bit overkill in most situation.

tnt wrote:

As a side note for future projects: Reverse polarity protection with a PMOS is better than diodes, it avoids the voltage drop.

Yes.. how do you know that I have this on my agenda for several projects in the upcoming year?!
Already selected the good ol' IRLML6402 (and IRLML2244 as an alternative) for this job. It is a good idea to incorporate it in this project too.

Source to power supply
Drain to circuit
Gate connected to gnd through a pull down resistor.

Sorry to correct you, but: exchange drain and source, and it's gonna work! ;)

Only problem remaining ist VGSmax, (mentioned P-FETs: +-12V). To protect from higher reversed polarities, a Zener (5,1..10V) between gate/PD resistor and source will do the job.

Damnit, I googled it quickly to make sure I didn't have D/S reversed and manged to pick the one site that got it wrong :p ( https://www.electronicdesign.com/power/reverse-polarity-protection-automotive-design )

Hi, this is my first post here. I am making a system to send stereo audio over fiber using SFP modules. I came across your project here and had a few questions.

Has this system been tested in hardware and proven to work?

I was wondering if the levels from and to the SFP are correct using the driver and receiver you have chosen?

I think you guys have done a great job of documenting and illustrating your project! Thank you for putting it upmfor others to see. If you ever need any help, I have experience with FPGAs and Verilog programming plus board,level hardware design and love,to collaborate.

Yes the board with the lvds driver / receiver works fine (minus the missing resistor that's documented in the issue and possibly already fixed in the git).

ralph wrote:

Hi, this is my first post here. I am making a system to send stereo audio over fiber using SFP modules. I came across your project here and had a few questions.

Has this system been tested in hardware and proven to work?

I was wondering if the levels from and to the SFP are correct using the driver and receiver you have chosen?

I think you guys have done a great job of documenting and illustrating your project! Thank you for putting it up for others to see. If you ever need any help, I have experience with FPGAs and Verilog programming plus board level hardware design and love to collaborate.

Thanks for the quick info. I shall build one myself to test and will get back to you.

Hi ralph - welcome to the osmocom community!

The 'active' version (called 'SFP experimenter') has been deeply tested by tnt. Before we designed and tested it (see #3523 and #3524, also wiki page Sfp-experimenter ).

Another version w/o transceivers (called 'SFP breakout', see #3313) was also made, but did not went through intense testing yet; however, first tests as for its active twin have been made and proved this working too.

ralph wrote:

Thanks for the quick info. I shall build one myself to test and will get back to you.

It's not too much revelation to say that sysmocom thinks of running a small production batch for both PCBAs within this month. So you might want to wait until beginning of Feb'19... ;)

tnt wrote:

Yes the board with the lvds driver / receiver works fine (minus the missing resistor that's documented in the issue and possibly already fixed in the git).

It has been added, but not publicly committed yet. - Actually I integrated both a PD on RD_N and a possible PU on RD_P, as discussed. On the reverse polarity protection via p-FET: it has not been decided yet.

Hi all, is there a pdf or jpg or tiff of the schematic and pcb layers? I do not have Eagle, my design software is Pcad from Altium. Thanks.

laforge wrote:

I'd like to ask mschramm to add PDF renderings and gerber output files to the git repository. Thanks!

Gerbers for v1 have already been uploaded by you. Schematics for the upcoming version have just been pushed to the repo, and Eagle sch and brd as well as new Gerber follow.
Schematics have also been added as attachments in the SFP section of "Misc Hardware Projects" wiki pages.