You need to apply the following bodges:
=== enable frame generation by timer ===
Bridge TP10 PA20/Pin16/RF (Receive Frame) to TP14 PA27/Pin37/TIOB2 (Timer 2, IO B).
This supplies the timer-generated frame sync (TIOB2) to the SSC peripheral (RF).
Bridge TP16 PA29/Pin41/TCLK2 (ext. clock input 2 to timer) to PA19/Pin13/RK (Receive Clock).
Use the bottom of the PCB, TP16 is clearly visible, for RK use the via of the RK_CLK signal approx. 8mm left of it. (RK is an input
==== generate 2.048 Mhz master clock ====
Solder a 33R resistor over testpads TP4 and TP5 next to the IDT LIU (TP4=2.048MHz master clock to LIU, TP5=TX clock for serial LIU data). The serial perihperal (SSC) in the sam4s will generate the 2.048M bit clock, which we'll now also provide as the master clock to the LIU.
Therefore --> you can keep R19 unpopulated.
==== fix spi mode of LIU SPI ====
You probably want to lift up SCLKE on the LIU and connect it to Vcc. It's at GND on my board, but this way (as was the case in the old osmocom-e1-interface board) the SPI mode is different for RX and TX... (check figure fig 24, 25 and 26 on page 75 of the 82v2081 datasheet).
==== DAC / TCXO ===
For a first bringup (and mainly working on USB) it's sufficient to populate R36 and R42 the "analog section" (around the OPAmps), use only the internal DAC0 and the TCXO. I haven't worked on this section, either.
