Use SAMD XOSC / PLL / GCLK to allow lower reference frequencies
Dieter has suggested a feature to allow using a reference clock at lower frequencies, such as 1MHz.
This is too low to use as an input directly into the Si5351C. However, the XOSC of the SAMD allows for input frequencies down to 400kHz. The crystal oscillator can also be disabled, allowing logig-level clock input. Internal fractional PLL can be used to generate a clock up to 96 MHz from it, and that clocks can then be output via a GCLK block on any of the GCLK_IO pins.
The resulting output could be routed to the secondary input of the Si5351C. This way, we could support e.g. multiplying from 1 MHz to 10 MHz in the SAMD, and then drive the Si5351C as we would with a direct 10MHz reference.
I of course don't know how good the phase noise of the SAMD internal PLL is...
Additional information on what the clock chip can actually achieve is available at