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Bug #4187

traces on inner layer 3 perform a split of the VCC plane

Added by laforge about 1 month ago. Updated 28 days ago.

Status:
Resolved
Priority:
Normal
Assignee:
Target version:
-
Start date:
08/31/2019
Due date:
% Done:

100%


Description

normally, the inner two layers are supply planes and shouldn't be interrupted. The main reason for this is that they serve as return path for the signal traces on outer layers.

However, we now have four signals basically cutting the entire plane into half for almost the entire length of the board. We can actually see it quite nicely in the PDF preview from Eurocircuits:

This is problematic, particularly if any of the affected signals are fast or have steep edges.

Possible options are:
  • try to keep Layer3 traces short and bring them to the bottom layer as soon as possible
  • add stitching caps between GND and VCC layers to enable return current to switch between bottom (GND) and L3 (VCC) when the bottom signal trace crosses the L3 signal trace
vcc-split.png View vcc-split.png 34.4 KB laforge, 08/31/2019 05:02 PM
3844

History

#1 Updated by laforge about 1 month ago

  • Project changed from mPCIe WWAN modem USB breakout board to m.2 (NGFF) WWAN modem USB breakout board
  • Target version deleted (hw-v2)

#2 Updated by mschramm 28 days ago

  • Status changed from New to In Progress

#3 Updated by mschramm 28 days ago

  • Status changed from In Progress to Resolved
  • % Done changed from 0 to 100

fixed in aaaf260 .

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