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Feature #5063

Allow un-powered operation

Added by laforge 3 months ago. Updated 22 days ago.

Status:
Resolved
Priority:
Normal
Assignee:
Category:
electronics
Target version:
Start date:
03/09/2021
Due date:
% Done:

100%


Description

Right now, the OpenVizsla always needs to be powered. As soon as power is removed, the communication between host and device breaks down. We received reports that a simple diode can be added at one location in the design to prevenr this problem from happening.

Let's analyze this in detail and decide if the diode change can be applied to "master", or if we have to look for something more sophisticated, avoiding the voltage drop over a diode.

schematic change.jpg View schematic change.jpg 116 KB cibomahto, 05/22/2021 06:59 PM
suggested_targetVBUS_bott.png View suggested_targetVBUS_bott.png 535 KB mschramm, 05/23/2021 07:17 PM
2diodes_mock.gif View 2diodes_mock.gif 49.1 KB mschramm, 05/23/2021 08:22 PM
component placement.jpg View component placement.jpg 181 KB cibomahto, 05/24/2021 06:49 PM
TARGETVBUS as split plane.jpg View TARGETVBUS as split plane.jpg 406 KB cibomahto, 05/24/2021 07:06 PM
design rule.jpg View design rule.jpg 111 KB cibomahto, 05/24/2021 07:09 PM
c46-new.jpg View c46-new.jpg 24.3 KB mschramm, 05/25/2021 02:12 PM
targetVBUS-layerchange_top.jpg View targetVBUS-layerchange_top.jpg 32.9 KB mschramm, 05/25/2021 02:12 PM
move vias and clean VUSB trace.jpg View move vias and clean VUSB trace.jpg 288 KB cibomahto, 05/25/2021 02:55 PM
stitching-via.jpg View stitching-via.jpg 36.5 KB mschramm, 05/25/2021 09:23 PM
before.jpg View before.jpg 212 KB cibomahto, 05/26/2021 04:15 PM
after.jpg View after.jpg 234 KB cibomahto, 05/26/2021 04:15 PM
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Related issues

Related to OpenVizsla USB tracer/analyzer - Feature #5076: Update board revisionIn Progress

Blocks OpenVizsla USB tracer/analyzer - Feature #5160: Increase board revision to '3.4'Resolved05/22/2021

History

#1 Updated by mschramm 3 months ago

  • Status changed from New to In Progress
  • % Done changed from 0 to 10

Unfortunately no real news here yet. - We got an image showing a hand-soldered patch wire from nework "+5V" behind L2 connecting to "targetVBUS" - but no diode visible so far, maybe it's in series to L2 on the (non-imaged) PCBA top side. So this all looks like the unit is powered from the host all the time...? We'll inquire again.

#2 Updated by mschramm 3 months ago

  • Status changed from In Progress to Stalled

No news here by now.

#3 Updated by laforge 3 months ago

mschramm wrote:

No news here by now.

well, then maybe ask again the user who requested it :)

#4 Updated by mschramm 3 months ago

  • % Done changed from 10 to 20

We're going to merge the other solved design improvements and not wait for further details regarding this user requirement. - They came up with another 'problem' (not further specified) which they also solved with a diode, - but no schematics on either detail yet, maybe next week.

#5 Updated by mschramm 2 months ago

#6 Updated by mschramm 26 days ago

  • Status changed from Stalled to In Progress
  • Target version set to 3.4

#7 Updated by cibomahto 26 days ago

Changes requested:

  • introduce BAT60A diode between Vusb (from J1) and F1
  • introduce an alternative current path (also via BAT60A) between
    targetVBUS (from J2) and F1.

#8 Updated by cibomahto 26 days ago

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Here's a schematic for the requested change. The BAT60A parts are taken from the Altium content vault, and have an SOD323 footprint.

Waiting to hear from mschramm on where to place the tracks.

#9 Updated by mschramm 24 days ago

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Suggesting to use the inner layer 3 (sketch 'suggested_targetVBUS_bott.png' is bottom view): start is where target VBUS originates, and trace could end 'north' of the name plate, no too close to the USB shield.

Seen from top and name plate in reading orientation:

  • move F1, L2 and C46 more right
  • LD4 and R9 might be in the way, so move them too
  • you could flip C16 180°, so that its GND conn is close to the 1117's tap (C16 is too small for a 1117 anyway, so don't move it further away from the 1117)
  • use two vias when bring the target VBUS trace to the top layer

I think a good way is to directly let 'face' the two cathodes each other and bring that stub to F1. Maybe you don't need to move F1 and L2 that much right, you'll see. If you find by chance a way to let C16 come closer to the input of U9 (TLV1117-33), I'd appreciate. - C46 is nonsense anyway, so you can move around where it worries least.

#10 Updated by cibomahto 24 days ago

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Component positions seem fine- photo attached.

Putting TARGETVBUS on the inner layer requires drawing it as a polygonal split plane, because the layer is a special 'plane' layer type. I drew it so that the effective trace width would be similar to the other traces on the net, ~1.27mm. Unfortunately this isn't enforceable by DRC, however this shouldn't be a critical trace. I also added a specific design rule to make a direct connection between the plane and the pin on J2, as a thermal via wouldn't work correctly in that situation.

Checked in here: https://github.com/openvizsla/ov_ftdi/pull/48/commits/0020c958ba4ffb6fe848d9c11ef051b614e5ecc6

#11 Updated by mschramm 23 days ago

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Thanks! The rectangular caps of the new power trace look funny, but of course will work. Also I like the C46 position.

What should still be changed is

  • the leftmost via's position. It is a little too much left, and depending on the tolerances of the USB socket's shield and pressing force during (manual) soldering, a chance remains that they could touch. Please move this via slightly more right.
  • the C46 'south' connection has an arc from its wire trace which gives a warning on a potential clearance issue in the board house's parser. Maybe just delete this stub (or trace end) and satisfy the DRC by a narrower wire trace end just below the capacitor's land which won't have that huge arc.

#12 Updated by mschramm 23 days ago

mschramm wrote:

  • the leftmost via's position.

...of the targetVBUS power trace layer change land

#13 Updated by mschramm 23 days ago

also the new position of C16 is now much better than on the original in terms of stability of the 1117!

#15 Updated by mschramm 22 days ago

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The VBUS via position now makes me sleep much better, thanks! ,) Reduced copper on C46 is now done, too.

What is left here - sorry to notice this now and not before: the cathodes of the two diodes have no rounded pads. I guess it's because they came fresh from the lib, and here it's not about solder beads, but more a solder paste stencil cleaning issue. Please round these two pads.

New here is something we unfortunately already know: one of your stitching vias shows this inner layer restring issue... we had this in #5108#note-4 . This time it is the lower left via, of which I stated "Interestingly, the lower left via is even closer to the opening for that 'bridge trace', but does not show (yet) this problem... can't explain." Still can not explain whether it is a rounding error or what else...

The PCB house's parser notices this and shows as a warning. However, the overall result is 'green', as they obviously use a smaller tool diameter to make this via (0,05mm less if I interprete ther values right) - so I'd say let them do the repair.

So the only thing to do here are the rounded caps of the two cathodes' lands.

#16 Updated by mschramm 22 days ago

#17 Updated by cibomahto 22 days ago

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What is left here - sorry to notice this now and not before: the cathodes of the two diodes have no rounded pads. I guess it's because they came fresh from the lib, and here it's not about solder beads, but more a solder paste stencil cleaning issue. Please round these two pads.

Rounded the cathode pads of D1 and D2 using the strategy from: https://osmocom.org/issues/5078#note-1

Implemented here: https://github.com/openvizsla/ov_ftdi/pull/48/commits/34bf82ddd5c3e9628a2d07f6d4c1fa33cde8affb

As requested, the vias causing the inner layer restring issue have not been modified in the design file.

#18 Updated by mschramm 22 days ago

  • Status changed from In Progress to Resolved
  • % Done changed from 90 to 100

thanks - solved!

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