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laforge, 02/19/2016 10:48 PM
update with current plans for devel board

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= Our GSM Development Board =
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The idea is simple:
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 * We start with the Openmoko Calypso/Iota/Rita design
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 * We replace the actual digital baseband chip (Calypso) with a normal Blackfin DSP
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To recap the block schematic of the Calypso deign, we repeat it here:
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[[Image(wiki:OpenmokoCalypsoModemDesign:calypso-block.png)]]
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== Internal Interfaces ==
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Each of those interfaces is connected to the Blackfin+Spartan3E module:
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=== TWL3025 BSP ===
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This is a SPI port with read/write access to all TWL3025 internal registers.  However, in case of downlink Rx operation, the burst
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data is transferred over this port (which needs 8.66Mbps of the 13Mbps bandwidth).  It is clocked by CLK13M
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This typically connects to the Calypso BSP.
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=== TWL3025 USP ===
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This is a generic SPI port for read/write to all TWL3025 internal registers.  It is clocked by CLK13M
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=== TWL3025 TSP ===
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The Time Serial Port is clocked by CLK13M/2 and is a pure input port, i.e. a Frame and a Data-In line are sufficient.
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This typically connects to the Calypso TPU.
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This interface is used for sequencing the Rx/Tx operation of the baseband interface.
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=== TRF6151C TSP ===
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This is a serial interface with strobe (not chip select).
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It is mostly used to configure the PLL, PGA Gain and power of the transceiver.
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This typically connects to the Calypso TSP/TPU
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== Requirements ==
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This is an overview of the different applications for a GSM Devel Board and their requirements
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=== Requirements for the GSM MS side ===
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 * transmit and receive in one TS every frame
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 * retune Rx and Tx according to hopping sequence for every frame
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 * synchronize carrier clock, bitclock and frame with BTS
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=== Requirements for a GSM scanner ===
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 * two independent receivers, one on MS-Rx, the other on BTS-Rx side
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 * ability to start decoding at some point (PCH/AGCH/SDCCH) and then follow a given hopping sequence (MAIO) for one TCH
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 * ability to decrypt A51/A52 with user-provided Kc
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 * Jammer: possibly transmitting interference in the Tx slices of the victim
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 * synchronize carrier clock, bitclock and frame with BTS
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==== Possible implementation ====
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 * two TRF6151 in pure Rx configuration
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  * one for MS-Rx side
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  * other one for MS-Tx side
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 * two TWL3025 in pure Rx configuration
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 * both TWL3025 BSP permanently in downlink mode (I/Q samples)
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  * we get 2*( 2*16*270k) bps serial samples (7.33Mbps) input signal
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 * connect those two serial sample streams to CPU+DSP (blackfin?)
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 * forward demodulated/decoded samples to PC
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=== Requirements for a GSM BTS ===
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 * tune MS-Rx side to MS-Tx frequency
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 * tune MS-Tx side to MS-Rx frequency
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 * continuous Rx and Tx in all timeslots on one ARFCN
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 * ability to determine timing advance of Uplink frames
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==== Possible implementation ====
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 * Use two independent TRF6151 frontends one for uplink, one for downlink
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 * First TRF6151 will generate 26MHz and respect AFC from TWL3025
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 * Second TRF6151 will use 'external VTXCO' configuration from 26MHz clock
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