GsmDevelBoard » History » Version 6
laforge, 02/19/2016 10:48 PM
1 | 3 | laforge | = Our GSM Development Board = |
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2 | 1 | laforge | |
3 | 3 | laforge | The idea is simple: |
4 | * We start with the Openmoko Calypso/Iota/Rita design |
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5 | * We replace the actual digital baseband chip (Calypso) with a normal Blackfin DSP |
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6 | 1 | laforge | |
7 | 5 | laforge | The block diagram looks something like this: |
8 | 1 | laforge | |
9 | 5 | laforge | [[Image(gsmdevboard-block.png)]] |
10 | 1 | laforge | |
11 | 4 | laforge | We have a dedicated wiki page about the signals that need to be connected between RF board and DSP: [wiki:GsmDevelBoard/SignalsBetweenRFandDSP] |
12 | 1 | laforge | == Internal Interfaces == |
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14 | 3 | laforge | Each of those interfaces is connected to the Blackfin+Spartan3E module: |
15 | 1 | laforge | |
16 | === TWL3025 BSP === |
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17 | |||
18 | 6 | laforge | The [wiki:BasebandSerialPort Baseband serial Port] is a SPI port with read/write access to all TWL3025 internal registers. However, in case of downlink Rx operation, the burst |
19 | 1 | laforge | data is transferred over this port (which needs 8.66Mbps of the 13Mbps bandwidth). It is clocked by CLK13M |
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21 | This typically connects to the Calypso BSP. |
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22 | |||
23 | === TWL3025 USP === |
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24 | |||
25 | 6 | laforge | The [wiki:MicrocontrollerSerialPort Microcontroller Serial Port] is a generic SPI port for read/write to all TWL3025 internal registers. It is clocked by CLK13M |
26 | 1 | laforge | |
27 | === TWL3025 TSP === |
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28 | |||
29 | 6 | laforge | The [wiki:TimeSerialPort Time Serial Port] is clocked by CLK13M/2 and is a pure input port, i.e. a Frame and a Data-In line are sufficient. |
30 | 1 | laforge | |
31 | This typically connects to the Calypso TPU. |
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32 | |||
33 | This interface is used for sequencing the Rx/Tx operation of the baseband interface. |
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34 | |||
35 | === TRF6151C TSP === |
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36 | |||
37 | This is a serial interface with strobe (not chip select). |
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38 | |||
39 | It is mostly used to configure the PLL, PGA Gain and power of the transceiver. |
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40 | |||
41 | This typically connects to the Calypso TSP/TPU |
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42 | 3 | laforge | |
43 | |||
44 | == Requirements == |
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45 | |||
46 | This is an overview of the different applications for a GSM Devel Board and their requirements |
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47 | |||
48 | === Requirements for the GSM MS side === |
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49 | |||
50 | * transmit and receive in one TS every frame |
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51 | * retune Rx and Tx according to hopping sequence for every frame |
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52 | * synchronize carrier clock, bitclock and frame with BTS |
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53 | |||
54 | === Requirements for a GSM scanner === |
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55 | |||
56 | * two independent receivers, one on MS-Rx, the other on BTS-Rx side |
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57 | * ability to start decoding at some point (PCH/AGCH/SDCCH) and then follow a given hopping sequence (MAIO) for one TCH |
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58 | * ability to decrypt A51/A52 with user-provided Kc |
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59 | * Jammer: possibly transmitting interference in the Tx slices of the victim |
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60 | * synchronize carrier clock, bitclock and frame with BTS |
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61 | |||
62 | ==== Possible implementation ==== |
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63 | |||
64 | * two TRF6151 in pure Rx configuration |
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65 | * one for MS-Rx side |
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66 | * other one for MS-Tx side |
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67 | * two TWL3025 in pure Rx configuration |
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68 | * both TWL3025 BSP permanently in downlink mode (I/Q samples) |
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69 | * we get 2*( 2*16*270k) bps serial samples (7.33Mbps) input signal |
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70 | * connect those two serial sample streams to CPU+DSP (blackfin?) |
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71 | * forward demodulated/decoded samples to PC |
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72 | |||
73 | === Requirements for a GSM BTS === |
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74 | |||
75 | * tune MS-Rx side to MS-Tx frequency |
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76 | * tune MS-Tx side to MS-Rx frequency |
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77 | * continuous Rx and Tx in all timeslots on one ARFCN |
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78 | * ability to determine timing advance of Uplink frames |
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79 | |||
80 | ==== Possible implementation ==== |
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81 | |||
82 | * Use two independent TRF6151 frontends one for uplink, one for downlink |
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83 | * First TRF6151 will generate 26MHz and respect AFC from TWL3025 |
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84 | * Second TRF6151 will use 'external VTXCO' configuration from 26MHz clock |