GsmDevelBoard » History » Version 9
laforge, 02/19/2016 10:49 PM
outline
1 | 9 | laforge | {{>toc}} |
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2 | 1 | laforge | |
3 | 9 | laforge | h1. Our GSM Development Board |
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6 | 3 | laforge | The idea is simple: |
7 | 9 | laforge | * We start with the Openmoko Calypso/Iota/Rita design |
8 | * We replace the actual digital baseband chip (Calypso) with a normal Blackfin DSP |
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9 | 1 | laforge | |
10 | The block diagram looks something like this: |
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11 | |||
12 | [[Image(gsmdevboard-block.png)]] |
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15 | 9 | laforge | h2. Components |
16 | 1 | laforge | |
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19 | 9 | laforge | h3. BF537 Blackfind DSP |
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21 | 9 | laforge | |
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23 | h3. Xilinx Spartan-3E FPGA |
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26 | The [[GsmDevelBoardFPGA]] will host the following building blocks |
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27 | * [[GsmDevelBoardFPGA|TPU Interface]] |
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28 | * [[GsmDevelBoardFPGA|13MHz clock generation]] |
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31 | h2. Internal Interfaces |
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34 | 7 | laforge | Each of those interfaces is connected to the Blackfin+Spartan3E module. |
35 | 1 | laforge | |
36 | 9 | laforge | We have a dedicated wiki page about the signals that need to be connected between RF board and DSP: [[GsmDevelBoardSignalsBetweenRFandDSP]] |
37 | 1 | laforge | |
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39 | 9 | laforge | h3. TWL3025 BSP |
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42 | The [[BasebandSerialPort|Baseband serial Port]] is a SPI port with read/write access to all TWL3025 internal registers. However, in case of downlink Rx operation, the burst |
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43 | 1 | laforge | data is transferred over this port (which needs 8.66Mbps of the 13Mbps bandwidth). It is clocked by CLK13M |
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45 | This typically connects to the Calypso BSP. |
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48 | 9 | laforge | h3. TWL3025 USP |
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51 | 9 | laforge | The [[MicrocontrollerSerialPort|Microcontroller Serial Port]] is a generic SPI port for read/write to all TWL3025 internal registers. It is clocked by CLK13M |
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53 | 9 | laforge | |
54 | h3. TWL3025 TSP |
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55 | |||
56 | |||
57 | The [[TimeSerialPort|Time Serial Port]] is clocked by CLK13M/2 and is a pure input port, i.e. a Frame and a Data-In line are sufficient. |
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59 | 1 | laforge | This typically connects to the Calypso TPU. |
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61 | This interface is used for sequencing the Rx/Tx operation of the baseband interface. |
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64 | 9 | laforge | h3. TRF6151C TSP |
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67 | 1 | laforge | This is a serial interface with strobe (not chip select). |
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69 | It is mostly used to configure the PLL, PGA Gain and power of the transceiver. |
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70 | |||
71 | This typically connects to the Calypso TSP/TPU |
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75 | 9 | laforge | h2. Requirements |
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78 | 1 | laforge | This is an overview of the different applications for a GSM Devel Board and their requirements |
79 | 3 | laforge | |
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81 | 9 | laforge | h3. Requirements for the GSM MS side |
82 | 3 | laforge | |
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84 | 9 | laforge | * transmit and receive in one TS every frame |
85 | * retune Rx and Tx according to hopping sequence for every frame |
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86 | * synchronize carrier clock, bitclock and frame with BTS |
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87 | 3 | laforge | |
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89 | 9 | laforge | h3. Requirements for a GSM scanner |
90 | 3 | laforge | |
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92 | 9 | laforge | * two independent receivers, one on MS-Rx, the other on BTS-Rx side |
93 | * ability to start decoding at some point (PCH/AGCH/SDCCH) and then follow a given hopping sequence (MAIO) for one TCH |
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94 | * ability to decrypt A51/A52 with user-provided Kc |
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95 | * Jammer: possibly transmitting interference in the Tx slices of the victim |
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96 | * synchronize carrier clock, bitclock and frame with BTS |
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97 | 3 | laforge | |
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99 | 9 | laforge | h4. Possible implementation |
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102 | * two TRF6151 in pure Rx configuration |
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103 | ** one for MS-Rx side |
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104 | ** other one for MS-Tx side |
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105 | * two TWL3025 in pure Rx configuration |
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106 | * both TWL3025 BSP permanently in downlink mode (I/Q samples) |
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107 | ** we get 2*( 2*16*270k) bps serial samples (7.33Mbps) input signal |
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108 | * connect those two serial sample streams to CPU+DSP (blackfin?) |
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109 | * forward demodulated/decoded samples to PC |
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110 | |||
111 | |||
112 | h3. Requirements for a GSM BTS |
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113 | |||
114 | |||
115 | * tune MS-Rx side to MS-Tx frequency |
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116 | * tune MS-Tx side to MS-Rx frequency |
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117 | * continuous Rx and Tx in all timeslots on one ARFCN |
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118 | * ability to determine timing advance of Uplink frames |
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120 | |||
121 | h4. Possible implementation |
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124 | * Use two independent TRF6151 frontends one for uplink, one for downlink |
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125 | * First TRF6151 will generate 26MHz and respect AFC from TWL3025 |
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126 | * Second TRF6151 will use 'external VTXCO' configuration from 26MHz clock |