HardwareCalypso » History » Version 3
laforge, 02/19/2016 10:48 PM
add memory map information
1 | 1 | laforge | = Calypso Digital Baseband = |
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3 | The Calypso Digital Base Band chip is a popular DBB implementation for inexpensive feature phones. |
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5 | == Variants == |
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6 | * Calypso G2 C035 |
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7 | * Calypso G2 C035 Lite (D751749GHH) |
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8 | * Like C035, only 256kBytes of internal memory |
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9 | 2 | laforge | |
10 | 3 | laforge | == Memory Map == |
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12 | * nCS0 0x0000'0000 ... 0x007f'ffff (C132: external NOR flash) |
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13 | * nCS6 0x0080'0000 ... 0x00bf'ffff (internal SRAM, in case of calypso lite only 256kBytes) |
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14 | * nCS1 0x0100'0000 ... 0x017f'ffff (C123: external SRAM) |
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15 | 2 | laforge | |
16 | == Integrated Peripherals == |
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18 | === I2C Controller === |
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20 | The controller has two oddities: |
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21 | * It assumes that the peripheral has an address byte. If your peripheral doesn't, you have to |
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22 | write the first byte into the address register and not the FIFO |
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23 | * You cannot under-fill the FIFO, i.e. if you write 8 bytes into the 16byte deep fifo, the controller |
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24 | will transmit 16 bytes rather than 8. Therefore, always limit the FIFO depth to your write size! |
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25 | More details about this can be seen at [wiki:CalypsoI2CFIFO] |