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iCE40 E1 USB interface

This page is the main entry point for the (completed!) "Software defined" E1 USB interface using the iCE40 FPGA at its core.

Architecture

This approach tries to implement as much as possible inside an iCE40 FPGA

Particularly, the iCE40 FPGA
  • contains the E1 PHY. There is no external LIU*, reducing the BOM cost significantly. Instead, the comparators of the FPGA are used to detect RX positive / negative pulses and normal CMOS drivers to generate the TX pulses. In practice, this has shown to work reliably on short E1 links of a few meters. We'd expect some problems in terms of long-haul E1 links, but those are not really the target use case here.
  • contains the E1 framer, including frame alignment, CRC4 verification/generation, ...
  • contains a USB softcore (no external USB PHY needed)
  • contains a PicoRV32 softcore to implement USB protocol handling and to connect the E1 softcore with the USB softcore

So all-in-all, we can build a USB-E1 interface from little more than an iCE40 FPGA and an E1 line transformer!

Current stack

  • The hardware for the first production version is documented in the https://git.osmocom.org/osmo-e1-hardware
  • The fpga gateware and associated embedded firmware is hosted in the same git repository. Some parts are in submodules (be sure to use recursive clone)
  • The userspace daemon that handles the USB communication is hosted at: https://git.osmocom.org/osmo-e1d
  • The support for this daemon interface to the rest of the cellular stack is merged in mainline libosmo-abis. Make sure you build it with --enable-e1d, though.

Availability

The fully assembled and tested icE1usb hardware is sold by sysmocom (product page, data sheet) an can be purchased from the webshop - hobbyist/community discounts are available.

Presentations

Status

Hardware

  • First proof of concept was done in 2018, based on manually wired protoboard to prove viability of the USB and E1 interface.
  • Several hand-wired pre-production prototypes based on iCEbreaker and iCEbreaker-bitsy have been assembled and used successfully from late 2018 to early 2020
  • A fully integrated single-board design with two E1 lines and a GPS-DO for E1 clock stability has been created by tnt in August 2020. After a couple of prototypes were built and tested, a first production run was made and should be available through the sysmocom shop.

Early Proof-of-Concept and Prototypes

Early Proof of concept
picture of iCEBreaker + external circuitry (transformer, ..)

Pre-production Prototype

Rev 1.0 production

Rev 1.0 Production PCB
Rev 1.0 Production Batch

Software

The full stack from gateware through firmware and host software has been tested and used in a variety of scenarios.

Credits

The development of FPGA softcores, firmware, PCB schematics, PCB layout and osmo-e1d was done by Sylvain Munaut (tnt).

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