IcE1usb » History » Version 14

Version 13 (tnt, 10/28/2020 08:04 PM) → Version 14/20 (tnt, 11/03/2020 01:29 PM)

h1. iCE40 E1 USB interface

This page is the main entry point for the (completed!) "Software defined" E1 USB interface using the iCE40 FPGA at its core.

h2. Architecture

This approach tries to implement as much as possible inside an iCE40 FPGA

Particularly, the iCE40 FPGA
* contains the E1 PHY. There is no external LIU*, reducing the BOM cost significantly. Instead, the comparators of the FPGA are used to detect RX positive / negative pulses and normal CMOS drivers to generate the TX pulses. In practice, this has shown to work reliably on short E1 links of a few meters. We'd expect some problems in terms of long-haul E1 links, but those are not really the target use case here.
* contains the E1 framer, including frame alignment, CRC4 verification/generation, ...
* contains a USB softcore (no external USB PHY needed)
* contains a PicoRV32 softcore to implement USB protocol handling and to connect the E1 softcore with the USB softcore

So all-in-all, we can build a USB-E1 interface from little more than an iCE40 FPGA and an E1 line transformer!

digraph G {
rankdir = LR;

BTS -> XFRM [label="E1"];
Linux [label="Linux\nOsmoBSC"];
subgraph cluster_A {
label = "iCE40 E1 USB Interface";
XFRM [label="Magnetics"];
XFRM -> Comparators [label="E1 (HDB3)"];

subgraph cluster_B {
label = "iCE40 FPGA";
Framer [label="E1 Framer\nSoftcore"];
RISCV [label="RISCV\nSoftcore"];
USB [label="USB\nSoftcore"];
Comparators -> Framer [label="E1 (Serial Bits)"];
Framer -> RISCV;
USB -> Linux [label="Frame-aligned raw\nbits over USB"];

h2. Current stack

* The hardware for the first production version is documented in the
* The fpga gateware and associated embedded firmware is hosted in the same git repository. Some parts are in submodules (be sure to use recursive clone)
* The userspace daemon that handles the USB communication is hosted at:
* The support for this daemon interface to the rest of the cellular stack is merged in mainline [[libosmo-abis:]]. Make sure you build it with @--enable-e1d@, though.

h2. Presentations

* Talk from OsmoCon 2018 about the Software Defined E1 project as a whole : attachment:osmocon_2018_e1.pdf
* Talk from OsmoDevCon 2019 about the iCE40 based solution specifically: attachment:osmodevcon_2019_e1.pdf
* "video recording of the iC40 based approach / OsmoDevCon 2019":

h2. Status

h3. Hardware

* First proof of concept was done in 2018, based on manually wired protoboard to prove viability of the USB and E1 interface.
* Several hand-wired pre-production prototypes based on iCEbreaker and iCEbreaker-bitsy have been assembled and used successfully from late 2018 to early 2020
* A fully integrated single-board design with two E1 lines and a GPS-DO for E1 clock stability has been created by @tnt in August 2020. After a couple of prototypes were built and tested, a first production run was made and should be available through the sysmocom shop.

h4. Early Proof-of-Concept and Prototypes


h4. Pre-production Prototype


h4. Rev 1.0 production


h3. Software

The full stack from gateware through firmware and host software has been tested and used in a variety of scenarios.

* gateware for the FPGA and firmware for the RISC-V softcore is available from and is buildable using the icestorm OSS toolchain
* The host software/driver is part of [[osmo-e1d:]], see the proejct page for related details. [[libosmo-abis:]] has been extended with [[osmo-e1d:]] support.

h2. Credits

The development of FPGA softcores, firmware, PCB schematics, PCB layout and osmo-e1d was done by Sylvain Munaut Munat (@tnt).
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