- Table of contents
This is a simple hardware project that aims to generate a reusable module for interfacing E1/T1/J1 lines from various custom FPGA/CPLD/microcontroller projects.
The board contains tranformers, the analog circuitry, the LIU (line interface unit), an oscillator as well as an integrated transceiver chip.
It exposes the control interface (SPI) as well as the decoded synchronous Rx/Tx bitstreams each on a 2x5pin header.
Framer, Multiplexer, HDLC decoder or anything like that is out-of-scope for now. The idea relaly is to provide an interface as low-level as possible.
One of the ideas is to create a "soft E1" interface, where the Rx/Tx bitstreams are interfaced with the SSC of an AT91SAM3S and subsequently passed into a PC via USB. The 2Mbps signal is very low-bandwidth, so that a pure software implementation should be absolutely no problem for todays computing power.
The project is in design phase. Initial design has finished, but needs to be reviewed. First prototype PCBs are evaluated since January 12, 2012
JP2: TDM interface¶JP2 contains the serial TDM bitstream + clock for Rx and Tx direction. The signals are
|2||nRST||low-active reset line, uC can reset the transceiver by pulling this low|
|4||LOS||Loss of Signal|
|5||TDN||Transmit Data Negative|
|7||TD/TDP||Transmit Data / Transmit Data Positive|
|8||RD/RDP||Receive Data / Receive Data Positive|
|9||TCLK||Transmitter Clock. Depending on JP9, this is an input into the board, or an output|
|10||RDN/CV||Receive Data Negative / Code Violation|
JP1: SPI control¶
This is how the external microcontroller can control the transceiver chip.
|1||VCC_IN||Vcc input, board can be supplied form here if SJ2 is closed|
|4||nINT||low-active interrupt output, when transceiver wants to interrupt uC""|
|7||SDO||Serial Data Out (MISO)|
|8||SDI||Serial Data In (MOSI)|
|10||nCS||low-active chip-select of the SPI|
JP10 switches the master clock (MCLK) of the transceiver between two on-board oscillators
of 2.048 MHz and 1.544 MHz. This is required for selecting between E1 or T1/J1 mode.
|1-2||2.048 MHz (E1) mode|
|2-3||1.544 MHz (T1/J1) mode|
This jumper decides if the 2.048/1.544 MHz MCLK should also be used as TDM Transmit Clock.
|closed||use MCLK as TCLK source, TCLK pin on JP2 is output|
|open||external circuit provides TCLK on JP2|
JP3 + JP4¶
JP3can be used to supply power to the board.
show me the code¶
- make ridiculously large test pads smaller
- move C1 closer to U1 VDDIO pad (19)
- remove $ sign from component names
- define which value C5 should use
- mark pin 1 of J1 / J2 on copper + silk screen
- different footprint for L1 ? value ?
- JP10 is a big too close to J1
- J1 is too close to J2; it's not possible to attach two standard IDC cable connectors
- implement minimal SPI driver to initialize transceiver chip
Updated by laforge 8 months ago · 22 revisions