XMU 02 » History » Revision 2
Revision 1 (laforge, 11/07/2020 08:36 AM) → Revision 2/3 (laforge, 11/07/2020 08:39 AM)
h1. XMU 02
The XMU 02 seems to be some kind of CPRI front-haulmultiplexor. It appears to be used in situations where a (small number of) high-bitrate CPRI links from the DU is to be de-multiplexed to multiple more lower-bitrated CPRI links towards the RU.
It appears to be controlled via some RS485 based control channel. There are three MAX3485 transcevers for each of the three RJ45 connectors on the front (A1, A2, A3).
h2. Internal structure
h3. FPGA
Internally, it appears to be one large (44x44mm, >= 42x42 ball BGA) part, probably a FPGA, connected to the 14 SFP+ slots for CPRI.
Next to the FPGA are two "SN74CB3T16211":https://www.ti.com/lit/ds/symlink/sn74cb3t16211.pdf?ts=1604653662200&ref_url=https%253A%252F%252Fwww.ti.com%252Fsitesearch%252Fdocs%252Funiversalsearch.tsp%253FsearchTerm%253Dsn74cb3t16211 24bit bus-switch/level-shifters.
h3. SoC
There's a control SoC ("Ericsson ROP 101 1190/2") with FLASH + RAM
* Intel/Micron/Numonyx "RC48F4400P0VB0E":https://www.digchip.com/datasheets/download_datasheet.php?id=7512107&part-number=RC48F4400P0VB0E 512Mbit/64MByte NOR flash
* ISSI "IS42S32800D-7TLI":http://www.issi.com/WW/pdf/42-45S32800D.pdf 256MBit/32MByte SDRAM
h3. Clocking
There are three clock sections,
* Two seemingly identical sections comprised of
** "ERC3105E 491.52" Part (491.52 MHz?)
** "AD9510 Clock Distribution/PLL IC":https://www.analog.com/media/en/technical-documentation/data-sheets/AD9510.pdf
** "MAX8869 LDO":https://www.maximintegrated.com/en/products/power/linear-regulators/MAX8869.html
* One section consisting of
** VDSCLD 63.897 (63.897 MHz?)
** "AD9510 Clock Distribution/PLL IC":https://www.analog.com/media/en/technical-documentation/data-sheets/AD9510.pdf
** "MAX8869 LDO":https://www.maximintegrated.com/en/products/power/linear-regulators/MAX8869.html
