Retronetworking » Retro-GSM

h1. TCSM2 TRCO card

The TRCO card (Transcoder Controller) is the central brain of a Nokia TCSM2 unit. Each TCSM2 unit has one TRCO card sitting in [[TCSM2_TC1C_chassis|TC1C chassis]]; this card communicates with and controls all TR16/TR12 [[TCSM2_transcoder_cards|transcoder DSP cards]] sitting in the same chassis (communication across TC1C backplane), and it also communicates with and controls all associated [[TCSM2_ET_modules|Exchange Terminal modules]] that are only reachable via an [[TCSM2_interchassis_cable|interchassis cable]].

h2. CPU and adjacent peripherals

The CPU on the TRCO card is 80186, specifically Intel TN80C186EB20. The UART that is brought out to the RS-232 management port on the front of the module is contained inside the 80186 SoC (it has two UARTs), but the HDLC controllers are external: two Infineon SAB 82525 chips (2x HDLC) and one SAB 82526 (1x HDLC), for a total of 5 HDLC channels. (4 HDLC channels are used to talk to local CPUs of [[TCSM2_ET_modules|ET modules]], and one is used to talk in-band management to the BSC.)

h2. RAM, ROM and flash

The structure of non-volatile memory on this board is peculiar:

# There is 512 KiB of physically immutable program code in an OTP ROM chip, ST M27C4002. Ordinarily an immutable ROM of this type would be a boot ROM, but 512 KiB is awfully big for just a bootloader. From looking at system boot messages on the RS-232 port, it appears that the code in this "boot" PROM is powerful enough to establish communication with the BSC if that link is present and working, presumably to allow the BSC to push remote updates to the operational code in flash.

# There is 1 MiB of NOR flash memory, implemented in 8 AM29F010B-120JC chips, presumably wired in pairs across the 16-bit data bus. All update-able firmware components and all non-volatile system configuration must be stored in this flash.

The RAM size is modest in comparison: only 256 KiB, implemented in 2 Samsung K6T1008C2E-GL70 chips.

The first observation that can be made from looking at these memory sizes is that at least the big flash cannot be directly mapped. The total address space of 80186 is only 1 MiB, same as the original 8086, hence if the 1 MiB flash were directly mapped, there would be no address space left for RAM or for the 512 KiB boot PROM. Hence the flash mapping must be bank-switched (likely in 4 banks of 256 KiB each), and it is possible that the boot PROM may not rigidly occupy half of the address space either.