Retronetworking » Retro-GSM

h1. TCSM2 timing structure

h2. Hierarchical timing in TDM-based GSM

The TDM-based GSM architecture in which Nokia TCSM2 constitutes just one component (sitting between MSC and BSC) was designed to work with hierarchical timing: each network element normally synchronizes itself to its upstream, i.e., to the network element just above it in the hierarchy, instead of operating with a free-running clock. (If a network element operates with its own free-running clock, no matter how stable, its interoperation with other network elements becomes plesiochronous, which is the opposite of hierarchical timing.) In the hierarchical timing architecture, the TCSM synchronizes ("slaves") its timing to that received from the MSC, the BSC synchronizes its timing to that received from the TCSM (ultimately coming from the MSC by way of TCSM), and the BSC then passes this network timing to the individual BTSes which use their incoming E1 timing for everything, including RF carrier generation. (Presumably the MSC likewise synchronizes itself to higher-order timing coming from the fixed, non-mobile PSTN, but this part is out-of-scope for BSS and TCSM timing.)

h2. How Nokia TCSM2 does hierarchical timing

For each "unit" of TCSM2, there are between 1 and 7 E1 circuits going to the MSC (A interface) and one E1 circuit going to the BSC (Ater interface). TCSM2 is able to synchronize ("slave") its timing block to any of the MSC-side E1 circuits (one can configure the priority order as to which E1 circuit's timing takes precedence, with lower-priority circuits acting as fallback timing sources when the preferred one is down); once the timing block inside TCSM2 is synchronized to a particular E1 input, _all_ E1 outputs from that TCSM2 unit (the Ater output and _all_ outputs toward the MSC) follow that timing. The BSC is expected to obey the timing from the TCSM, and to talk back to TCSM with that timing. The practical implications are:

* Whichever MSC-side E1 circuit is selected as the timing master, the TCSM2 unit effectively acts as a loop-timed slave on that E1;

* The timing derived from the "master" E1 circuit is used to drive the timing on _all other_ E1 outputs from the same TCSM2 unit;

* All other E1 inputs to that TCSM2 must follow the same timing as the chosen master, otherwise E1 frame streams taken from those inputs will be subject to slips.

h2. Implications for a lab setup

In a lab setup that has neither an MSC nor a BSC, but instead connects both A and Ater E1 interfaces out of TCSM2 to a test rig, that test rig needs to meet the following requirements:

* It needs to be a timing master, i.e., it must not take its timing from the connected TCSM2 unit;

* The two E1 outputs from the test rig must have the same timing, or derive their timing from a common source.

In the current state of retronetworking (mid-late 2024), the easiest way to satisfy these requirements is to use [[e1-t1-adapter:icE1usb]] as the interface device, and to use both E1 ports on that adapter (which obey the icE1usb device's internal timing, ideally GPS-disciplined) to connect A and Ater.