PCIeSDR » History » Revision 2
Revision 1 (XK1ZU, 09/08/2020 10:18 PM) → Revision 2/3 (laforge, 09/11/2020 08:21 AM)
h1. PCIeSDR PCIeSDR boards are primarily supplied with Amarisoft solutions. The hardware exists in several variants which differ in the available bandwidth or the number of Rx / Tx ports. There is also a variant with a CPRI interface. There is available integrated GPS for precise time and frequency synchronization. Clock / PPS input and output is also available. The hardware Hardware is a closed source. The FPGA gateware is provided only comes in binary form. Drivers for the Linux system are supplied in the form of sources including build and installation script. The script.The higher-level driver (in userspace) includes a DSP, a calibration stage, and the gateware update. It is in the form of a closed source dynamic library named libsdr.so. The C API for Linux / x86 is in the form of a header file libsdr.h which also serves as brief documentation. h2. PCIeSDR MIMO 2x2 card Frequency range: 70 MHz to 6.0 GHz RF bandwidth: <200 kHz to 56 MHz RF power output <10 dBm 4 SMA female (Tx1-Tx2-Rx1-Rx2) 1 SMA female (GPS antenna with DC power supply) 2 internal 5-pin connectors for inter-card time synchronization PCIe gen2 X1 Based on AD9361 / FPGA Artix7 / LiteX and the ecosystem of cores h2. PCIeSDR MIMO 4x4 card PCIe gen2 X4 Based on AD937X (JESD204B) / FPGA Artix7 / LiteX and the ecosystem of cores h2. References * https://web.archive.org/web/20151027200938/http://www.amarisoft.com/document/SDR-MIMO-PCIe-Card.pdf * http://enjoy-digital.fr
