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Bug #3857

Use SAMD XOSC / PLL / GCLK to allow lower reference frequencies

Added by laforge 26 days ago. Updated 13 days ago.

Status:
In Progress
Priority:
Normal
Assignee:
Target version:
Start date:
03/24/2019
Due date:
% Done:

10%


Description

Dieter has suggested a feature to allow using a reference clock at lower frequencies, such as 1MHz.

This is too low to use as an input directly into the Si5351C. However, the XOSC of the SAMD allows for input frequencies down to 400kHz. The crystal oscillator can also be disabled, allowing logig-level clock input. Internal fractional PLL can be used to generate a clock up to 96 MHz from it, and that clocks can then be output via a GCLK block on any of the GCLK_IO pins.

The resulting output could be routed to the secondary input of the Si5351C. This way, we could support e.g. multiplying from 1 MHz to 10 MHz in the SAMD, and then drive the Si5351C as we would with a direct 10MHz reference.

I of course don't know how good the phase noise of the SAMD internal PLL is...

History

#1 Updated by laforge 26 days ago

  • Target version set to hw-v2

#3 Updated by laforge 13 days ago

  • Status changed from New to In Progress
  • % Done changed from 0 to 10

Most likely candidate is a ATSAMD21E18A-MUT which is in QFN-32 package (current: QFN-24) and has 256k flash and 32kBytes of RAM. It's readily available from e.g.Digikey in large volume.

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