Use SAMD XOSC / PLL / GCLK to allow lower reference frequencies
Dieter has suggested a feature to allow using a reference clock at lower frequencies, such as 1MHz.
This is too low to use as an input directly into the Si5351C. However, the XOSC of the SAMD allows for input frequencies down to 400kHz. The crystal oscillator can also be disabled, allowing logig-level clock input. Internal fractional PLL can be used to generate a clock up to 96 MHz from it, and that clocks can then be output via a GCLK block on any of the GCLK_IO pins.
The resulting output could be routed to the secondary input of the Si5351C. This way, we could support e.g. multiplying from 1 MHz to 10 MHz in the SAMD, and then drive the Si5351C as we would with a direct 10MHz reference.
I of course don't know how good the phase noise of the SAMD internal PLL is...
Additional information on what the clock chip can actually achieve is available at
- Status changed from In Progress to Resolved
- % Done changed from 10 to 100
XA input of Si5351C is now connected to Cortex' PA10, which also can be GCLK_IO4. They are connected via a series resistor and a voltage divider of 47k/30k , as the XA input has V_max = 1,3V. Those two resistors are already in the BOM, and they give 1,286V at 3V3 input. The series resistor ahead of 47k might get little bigger than 0R.
PA14 is XIN, and is already routed to the GPIO expansion header (see #3858). As discussed with laforge, we simply don't have more PCB space for adding a RF-grade connector. maximum frequency on that pad is 32 MHz, so I think this is acceptable.
All external connections on this header and on UEXT will get additional TVS diodes added.