adapt differential traces' properties to intended layer built-up for upcoming production run
The layer stack-up of the orginal PCBAs differs to what we are going to produce. Changing the materials for the layer stack means no pooling option, so let's change the three differential pairs to the following values:
- wire track width: 0,184 mm
- wire track spacing 0,194 mm
These values here result in characteristic impedance of 50 Ohms and a minimum differential impedance of 90 Ohms. Affected are the pairs
- TARGETDTAP_N / ~_P
- USB_N / ~_P
- TARGETD_N / ~_P
As discussed, please also make them a 'differential pair class'. We don't insist in sharp 45° angles, you might better want to go with bent traces.
The good news is that if the current design works with somewhat unmatched trace lengths and a nice T intersection, it should mean this is less critical than I might have imagined.
OK, but now we (you) can make it better! ;) Maintain a maximum pair lenght difference of less than 3,81mm (150mil), do a meander where the parallels are disturbed anyway, and not at a sane end. This might only be needed for TARGETDTAP_*, which unfortunately crosses a THT header. Don't introduce more vias on those traces.
If you want to 'play' with the inbuilt diff pair helper tool (or another tool of your choice): at 500 MHz, the material has an Er= 4,21. Layer distance (height of dielectricum) is 0,119mm, end copper is 35µm. And let me hear your results, if the Altium helper tool is far off the mentioned values.
- File differential pairs rule.png differential pairs rule.png added
- File matched length rule.png matched length rule.png added
- File targetd.png targetd.png added
- File targetdtap.png targetdtap.png added
- File usb.png usb.png added
- File altium_impedance_calculation differential.png altium_impedance_calculation differential.png added
- File altium_impedance_calculation_single.png altium_impedance_calculation_single.png added
First- the Altium calculator says that geometry is within ~5% of the 50/90 requirements, so no wild disagreement :-).
The following steps were performed:Schematic:
- Remove 'USB' net class
- Add 'USB' differential pair class, and add 3 USB sets to it
- Remove single-ended width rule for USB net class
- Add differential pairs routing rule for 'USB' differential pair class
- Add length matching rule for 'USB' differential pair class
- Re-route each differential pair, taking care to match lengths by adding meanders during the routing.
mschramm Before I check this in, can you take a look at the screen captures and give a preliminary approval/feedback? I can generate gerbers too, if you'd prefer.
- Status changed from New to In Progress
- % Done changed from 0 to 80
Thanks - now they're real USB traces, not just wires ;)
You placed some GND vias close to the TARGETD and TARGETDTAP layer changing vias - I suppose they are meant as GND stitching, that should do even without stitching caps.
One option for better ground plane continuity (without stitching caps) would be to make a small ground pour as a cut-out on the power layer, under the back-side USB signals. It's probably overkill for this design though.
- File restring-inner-layer1-stitching-vias-gerbv.jpg restring-inner-layer1-stitching-vias-gerbv.jpg added
- File restring-inner-layer1-stitching-vias.jpg restring-inner-layer1-stitching-vias.jpg added
After uploading the Gerbers to the PCB house, the profiler there throws two errors: two of the four new vias result in a too-small restring, 0,096mm instead of min. 0,125mm. However, it seems that by using a repair function, they accept it, but maybe then will not fully connected to the GND layer, which makes the vias useless then.
Interestingly, the lower left via is even closer to the opening for that 'bridge trace', but does not show (yet) this problem... can't explain.
Please move those two vias depicted as errors and the lower left stitching via slightly away so that we maintain the 0,125 restring.
I looked into adding a DRC rule for this again, however I don't see a way to add this. The issue is that because the inner layers are defined as 'planes', Altium doesn't generate annular rings for vias on those layers, which means there is nothing for the DRC to check. I also tried adding a via-to-geometry spacing rule, however I wasn't able to find a rule to match the cutouts generated around the non-ground signals. Switching these to 'polygon' layers allows for vias to be added, but is too big of a change.