GsmDevelBoardGsmDevelBoardFPGA » History » Revision 2
Revision 1 (laforge, 02/19/2016 10:48 PM) → Revision 2/5 (laforge, 02/19/2016 10:48 PM)
= The FPGA on the GSM Development Board = == Functional Blocks == === TPU === The TPU needs to drive the [wiki:TimeSerialPort Time Serial Port] for the [wiki:TWL3025] and [wiki:TRF6151], as well as some parallel I/O lines. ==== TSP of TRF6151 ==== The TSP to the TRF6151 uses three wires: * CLOCK (regular CLK_13M) * STROBE (generated by TPU) * DATA (provided by TPU at falling edge of CLOCK, TRF samples data at rising edge of CLOCK) [[Image(Rita:trf6151_serial_1.png)]] [[Image(Rita:trf6151_serial_2.png)]] ==== TSP of TWL3025 ==== The TSP of the TWL3025 usese three wires: * CLOCK (regular CLK_13M), the TSL3025 derives an internal CLK6.5 signal of half the clock rate and uses it for the TSP) * nTEN (TSP ENable) * TDR (sampled by TWL3025 at rising edge of CLK6.5) The CLK6.5 Signal makes things a bit more complicated than we would like. The sequence of events is something like: * CLK_13M is applied continuously to TSL3025 * nTEN is in default state of high (inactive) * internal CLK6.5 is in default state low * nTEN is asserted low by TPU, some 0..65ns before CLK_13M rising edge * next CLK13M falling edge starts first CLK6.5 rising edge * every falling edge of CLK13M toggles CLK6.5 * TDR is sampled at every rising edge of CLK6.5 (including the first edge above) * 7 bits are transferred during seven rising edges of CLK6.5 * TEN stays asserted for 1 CLK13M period after last bit is transferred * TEN needs to be released before next CLK13M rising edge to prevent another transfer [[Image(Iota:twl3025_tsp_serial.png)]] [[Image(wiki:Iota/twl3025_tsp_serial.png)]]
