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iCE40 E1 USB interface

This page is the main entry point for the (completed!) "Software defined" E1 USB interface using the iCE40 FPGA at its core.

Architecture

This approach tries to implement as much as possible inside an iCE40 FPGA

Particularly, the iCE40 FPGA
  • contains the E1 PHY. There is no external LIU*, reducing the BOM cost significantly. Instead, the comparators of the FPGA are used. In practice, this has shown to work on short E1 links of a few meters. We'd expect some problems in terms of long-haul E1 links, but those are not really the target use case here.
  • contains the E1 framer, including frame alignment, CRC4 verification/generation, ...
  • contains a USB softcore (no external USB PHY needed)
  • contains a PicoRISCV softcore to implement USB protocol handling and to connect the E1 softcore with the USB softcore

So all-in-all, we can build a USB-E1 interface from little more than an iCE40 FPGA and an E1 line transformer!

Current stack

Presentations

Status

Hardware

  • Several hand-wired pre-production prototypes based on iCEbreaker and iCEbreaker-bitsy or iCEpick have been assembled and used successfully in 2019 and early 2020
  • A fully integrated single-board design with two E1 lines and a GPS-DO for E1 clock stability has been created by tnt in August 2020; prototype boards exist, and we expect a first production run is imminent.

Early Prototype

picture of iCEBreaker + external circuitry (transformer, ..)

Pre-production Prototype

Software

The full stack from gateware through firmware and host software has been tested and used in a variety of scenarios.

Credits

The development of FPGA softcores, firmware, PCB schematics, PCB layout and osmo-e1d was done by Sylvain Munat (tnt).

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