Christian has posted a detailed status update to the osmocom-sdr mailing list, describing his progress with enhancing the sample rate from 500 kS/s to 4 MS/s (at 14 bits ADC). Also, some impedance mismatch between tuner and ADC was fixed.
The benefits of this are not only available to the users/customers of the next generation hardware, but there will be a stacking board to upgrade the existing OsmoSDR units.
The full details can be read in his mailing list post
At this point there is no ETA yet when the new design will be available,
There are something like 16 units of OsmoSDR that we have produce and which are able to sell to interested developers.
However, as there are only 16 units right now, and as the firmware and host software is in a barely usable but incomplete state, we would like to make sure that those 16 units get sold to people who actually have an interest (and expect to have at least some time time!) to fix and improve the current shortcomings.
So if you want to be among the first 16, I suggest you contact me at Harald Welte <laforge@…> and include a short description of who you are (if you are not a Osmocom regular) as well as some incidcation that you are actually going to work on improving the code. If you already know an area that you'd like to work on, please state that, too.
The price will be 180 EUR incl. VAT (that's 151.26 EUR without), i.e. the same price as for the units that will later be sold openly.
I have put together a wiki page with the current status at Status to make you aware where we are and what is missing.
Thanks in advance for your willingness to be early users and help us to improve the codebase.
At 28c3, the OsmoSDR team was busy verifying the hardware design on the first prototypes.
The result can be summarized as:
- SAM3U is working, enumerates on USB and can be programmed via SAM-BA
- E4K tuner driver is working
- Si570 driver is working
- FPGA can be flashed via JTAG bit-banging from SAM3U
- FPGA and SAM3U can speak via SPI
However, there are at least two bugs:
- USB socket footprint pin-out was mirrored
- clock output level of Si570 doesn't match FPGA clock input specs (amplitude too low)
The issues have been worked around, and firmware + FPGA development has made progress.