PCIeSDR » History » Version 1

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XK1ZU, 09/08/2020 10:18 PM


PCIeSDR boards are primarily supplied with Amarisoft solutions.
The hardware exists in several variants which differ in the available bandwidth or the number of Rx / Tx ports. There is also a variant with a CPRI interface. There is available integrated GPS for precise time and frequency synchronization. Clock / PPS input and output is also available. Hardware is a closed source. The FPGA gateware comes in binary form. Drivers for the Linux system are supplied in the form of sources including build and installation script.The higher-level driver includes a DSP, a calibration stage, and the gateware update. It is in the form of a closed source dynamic library named The C API for Linux / x86 is in the form of a header file libsdr.h which also serves as brief documentation.

PCIeSDR MIMO 2x2 card

Frequency range: 70 MHz to 6.0 GHz
RF bandwidth: <200 kHz to 56 MHz
RF power output <10 dBm
4 SMA female (Tx1-Tx2-Rx1-Rx2)
1 SMA female (GPS antenna with DC power supply)
2 internal 5-pin connectors for inter-card time synchronization
PCIe gen2 X1
Based on AD9361 / FPGA Artix7 / LiteX and the ecosystem of cores

PCIeSDR MIMO 4x4 card

PCIe gen2 X4
Based on AD937X (JESD204B) / FPGA Artix7 / LiteX and the ecosystem of cores


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