UmTRX architecture

The LMS6002D FPRF ICs provide analogue filtering, VGAs, VCOs and mixers etc. in addition to performing digital conversion.

DC offset and IQ balance correction is implemented in the front-end in the FPGA.

Host connection is via gigabit Ethernet and samples along with timestamps and system settings such as frequency, gain and bandwidth, are encapsulated in VITA Radio Transport (VRT) packets.

Higher TX and RX sample rates are used in the front-end than in communication with the host, and half-band and CIC filters implemented in the FPGA are used to perform up/down-conversion, with amplitude correction in place pre (RX) and post (TX) filtering. This allows the frequency to be shifted within the original sample rate and without having to re-tune the LMS6002D transceiver.

After filtering, RX samples are immediately forwarded to the host by Ethernet packet router.

TX packets received from the host are buffered by a SRAM FIFO to help ensure that there are always samples to transmit.

RX samples are time-stamped and TX samples can be sent at a precise time, ensuring that TX and RX are perfectly aligned (this is critical for TDM systems).

High level

UmTRX block diagram


UmTRX FPGA architecture diagram

FPGA_structure.png - UmTRX FPGA architecture diagram (147 KB) 9600, 12/01/2013 07:01 PM

UmTRX.png - UmTRX block diagram (162 KB) 9600, 12/01/2013 07:24 PM