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cibomahto

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  • Registered on: 03/10/2021
  • Last connection: 04/11/2021

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04/11/2021

03:10 PM OpenVizsla USB tracer/analyzer Bug #5108: adapt differential traces' properties to intended layer built-up for upcoming production run
Addressed here: https://github.com/openvizsla/ov_ftdi/pull/46/commits/9b71bb21f332daa2bc5b6bf366d7049afa9eaed3
I l...

04/10/2021

04:02 PM OpenVizsla USB tracer/analyzer Bug #5109: reduce solder stop opening sizes for pads of U2, U4 and U7
Added here: https://github.com/openvizsla/ov_ftdi/pull/46/commits/c0fcfa320e103b58bdb92f53467fdd30a578d304
03:41 PM OpenVizsla USB tracer/analyzer Bug #5108: adapt differential traces' properties to intended layer built-up for upcoming production run
Checked in here: https://github.com/openvizsla/ov_ftdi/pull/46/commits/8fdac586dd75a2ae5cf676829d2842c6370b6f0c
On...

04/09/2021

09:41 PM OpenVizsla USB tracer/analyzer Bug #5109: reduce solder stop opening sizes for pads of U2, U4 and U7
This can be accomplished by adding a 'Solder mask expansion' rule that matches pads in U2,U4 and U7. Will apply after...
09:29 PM OpenVizsla USB tracer/analyzer Bug #5108: adapt differential traces' properties to intended layer built-up for upcoming production run
First- the Altium calculator says that geometry is within ~5% of the 50/90 requirements, so no wild disagreement :-)....

04/06/2021

05:56 PM OpenVizsla USB tracer/analyzer Feature #5076: Update board revision
_Please then tag this with 'v3.3' when it gets merged upstream (Harald: @tmbinc might need to do this?)_
I believe...
05:52 PM OpenVizsla USB tracer/analyzer Feature #5076: Update board revision
Implemented here: https://github.com/openvizsla/ov_ftdi/pull/46/commits/8289ce9d6d0fe8bfd663abc834f23487a805db31
I...

03/28/2021

05:29 PM OpenVizsla USB tracer/analyzer Bug #5098: exported 'ov_ftdi.DWG' appears to be a DXF file
That's interesting- it looks an artifact from translating from the earlier version of Altium. The exporter had 'DWG' ...
02:53 PM OpenVizsla USB tracer/analyzer Bug #5075: Possibly misleading component value labels on Silkscreen
Corrected here: https://github.com/openvizsla/ov_ftdi/pull/46/commits/eb9e5777476d5e0926ac9fa4d2bf60baa5e07f6d
02:14 PM OpenVizsla USB tracer/analyzer Feature #5095: export project in ASCII interchange format for other eCAD prgms
Added here: https://github.com/openvizsla/ov_ftdi/pull/46/commits/a979fb7da370f548ac48a5ad89c072b077786570
edit: a...

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