Hardware Projects » E1/T1 Hardware Interface (including icE1usb)

h1. E1 Specifications

h2. G.702 "Digital Hierarchy Bit Rates"

* describes the hierarchy of 64k/2048k/8448k/34368k/139264k and their T1 counterparts

h2. G.703 "Physical/electrical characteristics of hierarchical digital interface"

Section 11 describes the "E12" interface at 2048 kbit/s

* Nominal bit rate: 2048 kbit/s

* Bit rate accuracy: +/-50 ppm (+/-102.4 bit/s)

* Code: High density bipolar of order 3 (HDB3) (a description of this code can be found in Annex A)

* Overvoltage protection requirements: refer to [ITU-T K.20]

The RJ45 / twisted pair interface uses 120 ohms differential/symmetric signaling with a nominal peak voltage of 3V and a nominal space voltage of 0V

h2. G.704 "Synchronous frame structures used at 1544, 6312, 2048, 8448 and 44 736 kbit/s hierarchical levels"

Section 2.3 specifies the basic frame structure at 2048 kbit/s

* the basic frame consists of 256 bits, numbered 1 to 256

* the frame repetition rate is 8000 Hz

* bits 1..8 of the frame have special significance, they contain the frame alignment signal (FAS) and the S-bits

* an optional CRC-4 mechanism can be used in bit 1 of the frame, using so-called CRC-4 multiframes composed of 16 frames

Section 5.1 specifies the interface at 2048 kbit/s carrying 64 kbit/s channels

* each of the 64 kbit/s channels occupise 8 bits per timeslot, numbered 1..8

* 32 timeslots of each 8 bits form the basic frame (256bits) described above

* timeslot 0 (TS0) is used for frame alignment and signaling, as described above

* timeslot 1..31 are free for user data. 16 is typically used for signaling [not custom in GSM A-bis, but in general ISDN]

* timeslot 16 can be used for channel-associated signaling (CAS) [not used in context of GSM A-bis]

h2. G.706 "FRAME ALIGNMENT AND CYCLIC REDUNDANCY CHECK (CRC) PROCEDURES RELATING TO BASIC FRAME STRUCTURES DEFINED IN RECOMMENDATION G.704"

Section 4 specifies the Frame alignment and CRC procedures at 2048 kbit/s interface

* frame alignment is assumed lost when three consecutive incorrect frame alignment signals (FAS) are received

* frame alignment is assumed lost when bit 2 in TS0 in frmaes not containing the FAS has been received with an error on three consecutive occasions

The following procedure is recommended:

_When a valid frame alignment signal is detected in frame n, a check should be made to ensure that a frame alignment signal does not exist in frame n + 1, and also that a frame alignment signal exists in frame n + 2. Failure to meet one or both of these requirements should cause a new search to be initiated in frame n + 2._

h2. HDLC

In the signaling timeslots (typically 64k slots, sometimes 16k sub-slots), HDLC is used for framing.  It delimits the start and end of the octet and frame boundaries within the bitstream of the (sub)slot.  See "wikipedia":https://en.wikipedia.org/wiki/High-Level_Data_Link_Control for a general introduction into HDLC.

ISO/IEC 13239 specifies HDLC.

* "ISO/IEC 13239 in Online Browsing Platform of IEC":https://www.iso.org/obp/ui/#iso:std:iso-iec:13239:en

* "Official Homepage of ISO/IEC 13239":https://www.iso.org/standard/37010.html