Quectel RM500Q » History » Version 1
laforge, 10/13/2020 07:43 AM
| 1 | 1 | laforge | h1. Quectel RM500Q |
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| 4 | h2. Mechanical |
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| 6 | This is a 5G module in 3052 form factor. The length of the m2 slot of the ngff-breakout v2 unfortuantely is too short to properly mount it, but with a bit of adhesive mounting tape, it can be made work. See #4782. We will address this in a subsequent version of the ngff-breakout board. |
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| 8 | h2. USB |
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| 10 | It enumeratese as @2c7c:0800@, full lsusb see attached attachment:rm500q-lsusb.txt |
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| 12 | h2. PCIe |
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| 14 | Once enabled via AT command or eFuse, the RM500Q enumerates on PCIe: |
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| 16 | <pre> |
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| 17 | 01:00.0 Unassigned class [ff00]: Qualcomm Device 0306 |
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| 18 | Subsystem: Qualcomm Device 010c |
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| 19 | Flags: fast devsel |
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| 20 | Memory at fe500000 (64-bit, non-prefetchable) [size=4K] |
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| 21 | Memory at fe501000 (64-bit, non-prefetchable) [size=4K] |
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| 22 | Capabilities: [40] Power Management version 3 |
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| 23 | Capabilities: [50] MSI: Enable- Count=1/32 Maskable+ 64bit+ |
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| 24 | Capabilities: [70] Express Endpoint, MSI 00 |
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| 25 | Capabilities: [100] Advanced Error Reporting |
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| 26 | Capabilities: [148] Secondary PCI Express |
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| 27 | Capabilities: [168] Physical Layer 16.0 GT/s <?> |
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| 28 | Capabilities: [18c] Lane Margining at the Receiver <?> |
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| 29 | Capabilities: [19c] Transaction Processing Hints |
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| 30 | Capabilities: [228] Latency Tolerance Reporting |
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| 31 | Capabilities: [230] L1 PM Substates |
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| 32 | Capabilities: [240] Data Link Feature <?> |
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| 33 | 00: cb 17 06 03 02 00 10 00 00 00 00 ff 10 00 00 00 |
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| 34 | 10: 04 00 50 fe 00 00 00 00 04 10 50 fe 00 00 00 00 |
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| 35 | 20: 00 00 00 00 00 00 00 00 00 00 00 00 cb 17 0c 01 |
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| 36 | 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 |
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| 37 | </pre> |
