1 |
c62f5734
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Christian Daniel
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2 |
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[$GENERAL$]
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3 |
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INIT=Z
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4 |
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prefix=EDF_
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5 |
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user_names=no
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6 |
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edif2sdf_mapfile=
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7 |
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logfile=efd2vhd.log
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8 |
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9 |
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[$EXPORT$]
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10 |
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FMAP=NO
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11 |
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HMAP=NO
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12 |
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13 |
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[$properties$]
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14 |
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CYMODE=
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15 |
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INIT=
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16 |
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FD INIT=integer
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17 |
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FDC INIT=integer
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18 |
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FDCE INIT=integer
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19 |
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FDCE_1 INIT=integer
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20 |
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FDCP INIT=integer
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21 |
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FDCPE INIT=integer
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22 |
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FDCPE_1 INIT=integer
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23 |
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FDCP_1 INIT=integer
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24 |
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FDC_1 INIT=integer
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25 |
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FDD INIT=integer
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26 |
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FDDC INIT=integer
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27 |
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FDDCE INIT=integer
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28 |
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FDDCP INIT=integer
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29 |
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FDDCPE INIT=integer
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30 |
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FDDP INIT=integer
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31 |
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FDDPE INIT=integer
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32 |
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FDDRCPE INIT=integer
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33 |
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FDDRRSE INIT=integer
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34 |
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FDE INIT=integer
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35 |
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FDE_1 INIT=integer
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36 |
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FDP INIT=integer
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37 |
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FDPE INIT=integer
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38 |
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FDPE_1 INIT=integer
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39 |
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FDP_1 INIT=integer
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40 |
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FDR INIT=integer
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41 |
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FDRE INIT=integer
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42 |
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FDRE_1 INIT=integer
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43 |
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FDRS INIT=integer
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44 |
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FDRSE INIT=integer
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45 |
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FDRSE_1 INIT=integer
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46 |
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FDRS_1 INIT=integer
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47 |
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FDR_1 INIT=integer
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48 |
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FDS INIT=integer
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49 |
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FDSE INIT=integer
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50 |
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FDSE_1 INIT=integer
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51 |
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FDS_1 INIT=integer
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52 |
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FD_1 INIT=integer
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53 |
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FJKC INIT=integer
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54 |
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FJKCE INIT=integer
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55 |
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FJKP INIT=integer
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56 |
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FJKPE INIT=integer
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57 |
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FJKRSE INIT=integer
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58 |
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FJKSRE INIT=integer
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59 |
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FTC INIT=integer
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60 |
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FTCE INIT=integer
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61 |
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FTCLE INIT=integer
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62 |
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FTCLEX INIT=integer
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63 |
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FTP INIT=integer
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64 |
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FTPE INIT=integer
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65 |
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FTPLE INIT=integer
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66 |
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FTRSE INIT=integer
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67 |
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FTRSLE INIT=integer
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68 |
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FTSRE INIT=integer
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69 |
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FTSRLE INIT=integer
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70 |
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FTCP INIT=integer
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71 |
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GTPA1_DUAL RXPRBSERR_LOOPBACK_0=integer
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72 |
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GTPA1_DUAL RXPRBSERR_LOOPBACK_1=integer
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73 |
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GTXE1 RXPRBSERR_LOOPBACK=integer
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74 |
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IDDR INIT_Q1=integer
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75 |
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IDDR INIT_Q2=integer
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76 |
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IDDR2 INIT_Q0=integer
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77 |
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IDDR2 INIT_Q1=integer
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78 |
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IDDR_2CLK INIT_Q1=integer
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79 |
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IDDR_2CLK INIT_Q2=integer
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80 |
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IFD INIT=integer
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81 |
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IFD_1 INIT=integer
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82 |
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IFDI INIT=integer
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83 |
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IFDI_1 INIT=integer
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84 |
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IFDX INIT=integer
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85 |
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IFDX_1 INIT=integer
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86 |
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IFDXI INIT=integer
|
87 |
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IFDXI_1 INIT=integer
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88 |
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ILD INIT=integer
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89 |
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ILD_1 INIT=integer
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90 |
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ILDI INIT=integer
|
91 |
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ILDI_1 INIT=integer
|
92 |
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ILDX INIT=integer
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93 |
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ILDX_1 INIT=integer
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94 |
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ILDXI INIT=integer
|
95 |
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ILDXI_1 INIT=integer
|
96 |
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ISERDES INIT_Q1=integer
|
97 |
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ISERDES INIT_Q2=integer
|
98 |
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ISERDES INIT_Q3=integer
|
99 |
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ISERDES INIT_Q4=integer
|
100 |
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ISERDES SRVAL_Q1=integer
|
101 |
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ISERDES SRVAL_Q2=integer
|
102 |
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ISERDES SRVAL_Q3=integer
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103 |
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ISERDES SRVAL_Q4=integer
|
104 |
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ISERDES_NODELAY INIT_Q1=integer
|
105 |
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ISERDES_NODELAY INIT_Q2=integer
|
106 |
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ISERDES_NODELAY INIT_Q3=integer
|
107 |
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ISERDES_NODELAY INIT_Q4=integer
|
108 |
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ISERDES_NODELAY SRVAL_Q1=integer
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109 |
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ISERDES_NODELAY SRVAL_Q2=integer
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110 |
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ISERDES_NODELAY SRVAL_Q3=integer
|
111 |
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ISERDES_NODELAY SRVAL_Q4=integer
|
112 |
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LD INIT=integer
|
113 |
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LDC INIT=integer
|
114 |
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LDCE INIT=integer
|
115 |
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LDCE_1 INIT=integer
|
116 |
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LDCP INIT=integer
|
117 |
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LDCPE INIT=integer
|
118 |
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LDCPE_1 INIT=integer
|
119 |
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LDCP_1 INIT=integer
|
120 |
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LDC_1 INIT=integer
|
121 |
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LDE INIT=integer
|
122 |
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LDE_1 INIT=integer
|
123 |
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LDG INIT=integer
|
124 |
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LDP INIT=integer
|
125 |
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LDPE INIT=integer
|
126 |
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LDPE_1 INIT=integer
|
127 |
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LDP_1 INIT=integer
|
128 |
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LD_1 INIT=integer
|
129 |
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ODDR INIT=integer
|
130 |
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ODDR2 INIT=integer
|
131 |
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OFD INIT=integer
|
132 |
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OFD_1 INIT=integer
|
133 |
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OFDE INIT=integer
|
134 |
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OFDE_1 INIT=integer
|
135 |
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OFDI INIT=integer
|
136 |
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OFDI_1 INIT=integer
|
137 |
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OFDT INIT=integer
|
138 |
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OFDT_1 INIT=integer
|
139 |
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OFDX INIT=integer
|
140 |
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OFDX_1 INIT=integer
|
141 |
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OFDXI INIT=integer
|
142 |
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OFDXI_1 INIT=integer
|
143 |
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OSERDES INIT_OQ=integer
|
144 |
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OSERDES SRVAL_OQ=integer
|
145 |
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OSERDES INIT_TQ=integer
|
146 |
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OSERDES SRVAL_TQ=integer
|
147 |
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OSERDES INIT_OQ=integer
|
148 |
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OSERDES INIT_TQ=integer
|
149 |
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OSERDES SRVAL_OQ=integer
|
150 |
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OSERDES SRVAL_TQ=integer
|
151 |
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lut_function=
|
152 |
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eqn=
|
153 |
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INIT_00=
|
154 |
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INIT_01=
|
155 |
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INIT_02=
|
156 |
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INIT_03=
|
157 |
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INIT_04=
|
158 |
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INIT_05=
|
159 |
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INIT_06=
|
160 |
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INIT_07=
|
161 |
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INIT_08=
|
162 |
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INIT_09=
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163 |
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INIT_0A=
|
164 |
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INIT_0B=
|
165 |
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INIT_0C=
|
166 |
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INIT_0D=
|
167 |
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INIT_0E=
|
168 |
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INIT_0F=
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169 |
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|
170 |
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INIT_10=
|
171 |
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INIT_11=
|
172 |
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INIT_12=
|
173 |
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INIT_13=
|
174 |
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INIT_14=
|
175 |
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INIT_15=
|
176 |
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INIT_16=
|
177 |
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INIT_17=
|
178 |
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INIT_18=
|
179 |
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INIT_19=
|
180 |
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INIT_1A=
|
181 |
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INIT_1B=
|
182 |
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INIT_1C=
|
183 |
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INIT_1D=
|
184 |
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INIT_1E=
|
185 |
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INIT_1F=
|
186 |
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|
187 |
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INIT_20=
|
188 |
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INIT_21=
|
189 |
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INIT_22=
|
190 |
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INIT_23=
|
191 |
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INIT_24=
|
192 |
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INIT_25=
|
193 |
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INIT_26=
|
194 |
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INIT_27=
|
195 |
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INIT_28=
|
196 |
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INIT_29=
|
197 |
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INIT_2A=
|
198 |
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INIT_2B=
|
199 |
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INIT_2C=
|
200 |
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INIT_2D=
|
201 |
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INIT_2E=
|
202 |
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INIT_2F=
|
203 |
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|
204 |
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INIT_30=
|
205 |
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INIT_31=
|
206 |
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INIT_32=
|
207 |
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INIT_33=
|
208 |
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INIT_34=
|
209 |
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INIT_35=
|
210 |
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INIT_36=
|
211 |
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INIT_37=
|
212 |
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INIT_38=
|
213 |
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INIT_39=
|
214 |
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INIT_3A=
|
215 |
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INIT_3B=
|
216 |
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INIT_3C=
|
217 |
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INIT_3D=
|
218 |
|
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INIT_3E=
|
219 |
|
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INIT_3F=
|
220 |
|
|
|
221 |
|
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INIT_40=
|
222 |
|
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INIT_41=
|
223 |
|
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INIT_42=
|
224 |
|
|
INIT_43=
|
225 |
|
|
INIT_44=
|
226 |
|
|
INIT_45=
|
227 |
|
|
INIT_46=
|
228 |
|
|
INIT_47=
|
229 |
|
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INIT_48=
|
230 |
|
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INIT_49=
|
231 |
|
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INIT_4A=
|
232 |
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INIT_4B=
|
233 |
|
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INIT_4C=
|
234 |
|
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INIT_4D=
|
235 |
|
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INIT_4E=
|
236 |
|
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INIT_4F=
|
237 |
|
|
|
238 |
|
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INIT_50=
|
239 |
|
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INIT_51=
|
240 |
|
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INIT_52=
|
241 |
|
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INIT_53=
|
242 |
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INIT_54=
|
243 |
|
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INIT_55=
|
244 |
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INIT_56=
|
245 |
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INIT_57=
|
246 |
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INIT_58=
|
247 |
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INIT_59=
|
248 |
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INIT_5A=
|
249 |
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INIT_5B=
|
250 |
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INIT_5C=
|
251 |
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INIT_5D=
|
252 |
|
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INIT_5E=
|
253 |
|
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INIT_5F=
|
254 |
|
|
|
255 |
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INIT_60=
|
256 |
|
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INIT_61=
|
257 |
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INIT_62=
|
258 |
|
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INIT_63=
|
259 |
|
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INIT_64=
|
260 |
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INIT_65=
|
261 |
|
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INIT_66=
|
262 |
|
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INIT_67=
|
263 |
|
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INIT_68=
|
264 |
|
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INIT_69=
|
265 |
|
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INIT_6A=
|
266 |
|
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INIT_6B=
|
267 |
|
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INIT_6C=
|
268 |
|
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INIT_6D=
|
269 |
|
|
INIT_6E=
|
270 |
|
|
INIT_6F=
|
271 |
|
|
|
272 |
|
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INITP_00=
|
273 |
|
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INITP_01=
|
274 |
|
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INITP_02=
|
275 |
|
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INITP_03=
|
276 |
|
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INITP_04=
|
277 |
|
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INITP_05=
|
278 |
|
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INITP_06=
|
279 |
|
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INITP_07=
|
280 |
|
|
|
281 |
|
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LPM_TYPE=
|
282 |
|
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LPM_WIDTH=integer
|
283 |
|
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LPM_DIRECTION=
|
284 |
|
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P_WIDTH=
|
285 |
|
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P_OFFSET=
|
286 |
|
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CLKDV_DIVIDE=real
|
287 |
|
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DUTY_CYCLE_CORRECTION=bool
|
288 |
|
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WIDTH=integer
|
289 |
|
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DIVIDE1_BY=integer
|
290 |
|
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DIVIDE2_BY=integer
|
291 |
|
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TimingChecksOn=bool
|
292 |
|
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Xon=bool
|
293 |
|
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MsgOn=bool
|
294 |
|
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SEL_F500K=bool
|
295 |
|
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SEL_F16K=bool
|
296 |
|
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SEL_F490=bool
|
297 |
|
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SEL_F15=bool
|
298 |
|
|
|
299 |
|
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;added for virtex4 library
|
300 |
|
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CLKFX_DIVIDE=integer
|
301 |
|
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CLKFX_MULTIPLY=integer
|
302 |
|
|
CLKIN_DIVIDE_BY_2=bool
|
303 |
|
|
CLKIN_PERIOD=real
|
304 |
|
|
CLKOUT_PHASE_SHIFT=
|
305 |
|
|
CLK_FEEDBACK=
|
306 |
|
|
DCM_PERFORMANCE_MODE=
|
307 |
|
|
DESKEW_ADJUST=
|
308 |
|
|
DFS_FREQUENCY_MODE=
|
309 |
|
|
DLL_FREQUENCY_MODE=
|
310 |
|
|
FACTORY_JF=
|
311 |
|
|
STARTUP_WAIT=bool
|
312 |
|
|
PHASE_SHIFT=integer
|
313 |
|
|
MONITOR_MODE=
|
314 |
|
|
SIM_MONITOR_FILE=
|
315 |
|
|
JTAG_CHAIN=integer
|
316 |
|
|
INIT_OUT=integer
|
317 |
|
|
PRESELECT_I0=bool
|
318 |
|
|
PRESELECT_I1=bool
|
319 |
|
|
BUFR_DIVIDE=
|
320 |
|
|
DSS_MODE=
|
321 |
|
|
AREG=integer
|
322 |
|
|
B_INPUT=
|
323 |
|
|
BREG=integer
|
324 |
|
|
CARRYINREG=integer
|
325 |
|
|
CARRYINSELREG=integer
|
326 |
|
|
CREG=integer
|
327 |
|
|
LEGACY_MODE=
|
328 |
|
|
MREG=integer
|
329 |
|
|
OPMODEREG=integer
|
330 |
|
|
PREG=integer
|
331 |
|
|
SUBTRACTREG=integer
|
332 |
|
|
ALMOST_FULL_OFFSET=
|
333 |
|
|
ALMOST_EMPTY_OFFSET=
|
334 |
|
|
DATA_WIDTH=integer
|
335 |
|
|
FIRST_WORD_FALL_THROUGH=bool
|
336 |
|
|
REFCLKSEL=
|
337 |
|
|
SYNCLK1OUTEN=
|
338 |
|
|
SYNCLK2OUTEN=
|
339 |
|
|
CAPACITANCE=
|
340 |
|
|
IOSTANDARD=
|
341 |
|
|
DIFF_TERM=bool
|
342 |
|
|
ICAP_WIDTH=
|
343 |
|
|
DDR_CLK_EDGE=
|
344 |
|
|
INIT_Q1=
|
345 |
|
|
INIT_Q2=
|
346 |
|
|
INIT_Q3=
|
347 |
|
|
INIT_Q4=
|
348 |
|
|
SRTYPE=
|
349 |
|
|
IOBDELAY=
|
350 |
|
|
IOBDELAY_TYPE=
|
351 |
|
|
IOBDELAY_VALUE=integer
|
352 |
|
|
DRIVE=integer
|
353 |
|
|
SLEW=
|
354 |
|
|
INIT_BITSLIPCNT=
|
355 |
|
|
;INIT_CE= ;2 elems bit_vector
|
356 |
|
|
;INIT_RANK1_PARTIAL= ;5 elems bit_vector
|
357 |
|
|
;INIT_RANK2= ;6 elems bit_vector
|
358 |
|
|
;INIT_RANK3= ;6 elems bit_vector
|
359 |
|
|
BITSLIP_ENABLE=bool
|
360 |
|
|
DATA_RATE=
|
361 |
|
|
INTERFACE_TYPE=
|
362 |
|
|
NUM_CE=integer
|
363 |
|
|
SERDES_MODE=
|
364 |
|
|
SRVAL_Q1=
|
365 |
|
|
SRVAL_Q2=
|
366 |
|
|
SRVAL_Q3=
|
367 |
|
|
SRVAL_Q4=
|
368 |
|
|
INIT_LOADCNT=
|
369 |
|
|
SERDES_MODE=
|
370 |
|
|
DATA_RATE_OQ=
|
371 |
|
|
INIT_OQ=
|
372 |
|
|
;INIT_ORANK1= ;6 elems bit_vector
|
373 |
|
|
INIT_ORANK2_PARTIAL=
|
374 |
|
|
DATA_RATE_TQ=
|
375 |
|
|
TRISTATE_WIDTH=integer
|
376 |
|
|
INIT_TQ=
|
377 |
|
|
INIT_TRANK1=
|
378 |
|
|
SRVAL_OQ=
|
379 |
|
|
SRVAL_TQ=
|
380 |
|
|
EN_REL=bool
|
381 |
|
|
RST_DEASSERT_CLK=
|
382 |
|
|
DOA_REG=integer
|
383 |
|
|
DOB_REG=integer
|
384 |
|
|
INIT_A=
|
385 |
|
|
INIT_B=
|
386 |
|
|
INVERT_CLK_DOA_REG=bool
|
387 |
|
|
INVERT_CLK_DOB_REG=bool
|
388 |
|
|
RAM_EXTENSION_A=
|
389 |
|
|
RAM_EXTENSION_B=
|
390 |
|
|
READ_WIDTH_A=integer
|
391 |
|
|
READ_WIDTH_B=integer
|
392 |
|
|
SIM_COLLISION_CHECK=
|
393 |
|
|
SRVAL_A=
|
394 |
|
|
SRVAL_B=
|
395 |
|
|
WRITE_MODE_A=
|
396 |
|
|
WRITE_MODE_B=
|
397 |
|
|
WRITE_WIDTH_A=integer
|
398 |
|
|
WRITE_WIDTH_B=integer
|
399 |
|
|
SRVAL=
|
400 |
|
|
WRITE_MODE=
|
401 |
|
|
DISABLE_COLLISION_CHECK=bool
|
402 |
|
|
ALIGN_COMMA_WORD=integer
|
403 |
|
|
BANDGAPSEL=bool
|
404 |
|
|
CCCB_ARBITRATOR_DISABLE=bool
|
405 |
|
|
CHAN_BOND_LIMIT=integer
|
406 |
|
|
CHAN_BOND_MODE=
|
407 |
|
|
CHAN_BOND_ONE_SHOT=bool
|
408 |
|
|
;CHAN_BOND_SEQ_1_1= ;11 elems bit_vector
|
409 |
|
|
;CHAN_BOND_SEQ_1_2= ;11 elems bit_vector
|
410 |
|
|
;CHAN_BOND_SEQ_1_3= ;11 elems bit_vector
|
411 |
|
|
;CHAN_BOND_SEQ_1_4= ;11 elems bit_vector
|
412 |
|
|
CHAN_BOND_SEQ_1_MASK=
|
413 |
|
|
;CHAN_BOND_SEQ_2_1= ;11 elems bit_vector
|
414 |
|
|
;CHAN_BOND_SEQ_2_2= ;11 elems bit_vector
|
415 |
|
|
;CHAN_BOND_SEQ_2_3= ;11 elems bit_vector
|
416 |
|
|
;CHAN_BOND_SEQ_2_4= ;11 elems bit_vector
|
417 |
|
|
CHAN_BOND_SEQ_2_MASK=
|
418 |
|
|
CHAN_BOND_SEQ_2_USE=bool
|
419 |
|
|
CHAN_BOND_SEQ_LEN=integer
|
420 |
|
|
CLK_CORRECT_USE=bool
|
421 |
|
|
CLK_COR_8B10B_DE=bool
|
422 |
|
|
CLK_COR_MAX_LAT=integer
|
423 |
|
|
CLK_COR_MIN_LAT=integer
|
424 |
|
|
;CLK_COR_SEQ_1_2= ;11 elems bit_vector
|
425 |
|
|
;CLK_COR_SEQ_1_3= ;11 elems bit_vector
|
426 |
|
|
;CLK_COR_SEQ_1_4= ;11 elems bit_vector
|
427 |
|
|
CLK_COR_SEQ_1_MASK=
|
428 |
|
|
;CLK_COR_SEQ_2_1= ;11 elems bit_vector
|
429 |
|
|
;CLK_COR_SEQ_2_2= ;11 elems bit_vector
|
430 |
|
|
;CLK_COR_SEQ_2_3= ;11 elems bit_vector
|
431 |
|
|
;CLK_COR_SEQ_2_4= ;11 elems bit_vector
|
432 |
|
|
CLK_COR_SEQ_2_MASK=
|
433 |
|
|
CLK_COR_SEQ_2_USE=bool
|
434 |
|
|
CLK_COR_SEQ_DROP=bool
|
435 |
|
|
CLK_COR_SEQ_LEN=integer
|
436 |
|
|
COMMA32=bool
|
437 |
|
|
;COMMA_10B_MASK= ;10 elems bit_vector
|
438 |
|
|
;CYCLE_LIMIT_SEL= ;2 elems bit_vector
|
439 |
|
|
;DCDR_FILTER= ;3 elems bit_vector
|
440 |
|
|
DEC_MCOMMA_DETECT=bool
|
441 |
|
|
DEC_PCOMMA_DETECT=bool
|
442 |
|
|
DEC_VALID_COMMA_ONLY=bool
|
443 |
|
|
;DIGRX_FWDCLK= ;2 elems bit_vector
|
444 |
|
|
DIGRX_SYNC_MODE=bool
|
445 |
|
|
ENABLE_DCDR=bool
|
446 |
|
|
;FDET_HYS_CAL= ;3 elems bit_vector
|
447 |
|
|
;FDET_HYS_SEL= ;3 elems bit_vector
|
448 |
|
|
;FDET_LCK_CAL= ;3 elems bit_vector
|
449 |
|
|
;FDET_LCK_SEL= ;3 elems bit_vector
|
450 |
|
|
;LOOPCAL_WAIT= ;2 elems bit_vector
|
451 |
|
|
MCOMMA_32B_VALUE=
|
452 |
|
|
MCOMMA_DETECT=bool
|
453 |
|
|
OPPOSITE_SELECT=bool
|
454 |
|
|
PCOMMA_32B_VALUE=
|
455 |
|
|
PCOMMA_DETECT=bool
|
456 |
|
|
PCS_BIT_SLIP=bool
|
457 |
|
|
PMACLKENABLE=bool
|
458 |
|
|
PMACOREPWRENABLE=bool
|
459 |
|
|
PMA_BIT_SLIP=bool
|
460 |
|
|
POWER_ENABLE=bool
|
461 |
|
|
REPEATER=bool
|
462 |
|
|
;RXAFEEQ= ;9 elems bit_vector
|
463 |
|
|
;RXASYNCDIVIDE= ;2 elems bit_vector
|
464 |
|
|
RXBY_32=bool
|
465 |
|
|
;RXCDRLOS= ;6 elems bit_vector
|
466 |
|
|
RXCLK0_FORCE_PMACLK=bool
|
467 |
|
|
;RXCLKMODE= ;6 elems bit_vector
|
468 |
|
|
RXCPSEL=bool
|
469 |
|
|
RXCRCCLOCKDOUBLE=bool
|
470 |
|
|
RXCRCENABLE=bool
|
471 |
|
|
RXCRCINITVAL=
|
472 |
|
|
RXCRCINVERTGEN=bool
|
473 |
|
|
RXCRCSAMECLOCK=bool
|
474 |
|
|
;RXCYCLE_LIMIT_SEL= ;2 elems bit_vector
|
475 |
|
|
;RXDATA_SEL= ;2 elems bit_vector
|
476 |
|
|
RXDCCOUPLE=bool
|
477 |
|
|
RXDIGRESET=bool
|
478 |
|
|
RXDIGRX=bool
|
479 |
|
|
RXENABLE=bool
|
480 |
|
|
RXEQ=
|
481 |
|
|
RXFDCAL_CLOCK_DIVIDE=
|
482 |
|
|
;RXFDET_HYS_CAL= ;3 elems bit_vector
|
483 |
|
|
;RXFDET_HYS_SEL= ;3 elems bit_vector
|
484 |
|
|
;RXFDET_LCK_CAL= ;3 elems bit_vector
|
485 |
|
|
;RXFDET_LCK_SEL= ;3 elems bit_vector
|
486 |
|
|
RXLB=bool
|
487 |
|
|
;RXLKADJ= ;5 elems bit_vector
|
488 |
|
|
;RXLOOPCAL_WAIT= ;2 elems bit_vector
|
489 |
|
|
RXLOOPFILT=
|
490 |
|
|
RXOUTDIV2SEL_A=
|
491 |
|
|
RXOUTDIV2SEL_B=
|
492 |
|
|
RXPD=bool
|
493 |
|
|
RXPLLNDIVSEL=
|
494 |
|
|
RXPMACLKSEL=
|
495 |
|
|
;RXRCPADJ= ;3 elems bit_vector
|
496 |
|
|
RXRECCLK1_USE_SYNC=bool
|
497 |
|
|
;RXSLOWDOWN_CAL= ;2 elems bit_vector
|
498 |
|
|
RXTADJ=bool
|
499 |
|
|
RXUSRDIVISOR=integer
|
500 |
|
|
;RXVCODAC_INIT= ;10 elems bit_vector
|
501 |
|
|
RXVCO_CTRL_ENABLE=bool
|
502 |
|
|
RX_BUFFER_USE=bool
|
503 |
|
|
;RX_CLOCK_DIVIDER= ;2 elems bit_vector
|
504 |
|
|
RX_LOS_INVALID_INCR=integer
|
505 |
|
|
RX_LOS_THRESHOLD=integer
|
506 |
|
|
SAMPLE_8X=bool
|
507 |
|
|
SH_CNT_MAX=integer
|
508 |
|
|
SH_INVALID_CNT_MAX=integer
|
509 |
|
|
;SLOWDOWN_CAL= ;2 elems bit_vector
|
510 |
|
|
TXABPMACLKSEL=
|
511 |
|
|
;TXASYNCDIVIDE= ;2 elems bit_vector
|
512 |
|
|
TXCLK0_FORCE_PMACLK=bool
|
513 |
|
|
TXCLKMODE=
|
514 |
|
|
TXCPSEL=bool
|
515 |
|
|
TXCRCCLOCKDOUBLE=bool
|
516 |
|
|
TXCRCENABLE=bool
|
517 |
|
|
TXCRCINITVAL=
|
518 |
|
|
TXCRCINVERTGEN=bool
|
519 |
|
|
TXCRCSAMECLOCK=bool
|
520 |
|
|
;TXDATA_SEL= ;2 elems bit_vector
|
521 |
|
|
;TXDAT_PRDRV_DAC= ;3 elems bit_vector
|
522 |
|
|
;TXDAT_TAP_DAC= ;5 elems bit_vector
|
523 |
|
|
TXENABLE=bool
|
524 |
|
|
TXFDCAL_CLOCK_DIVIDE=
|
525 |
|
|
TXHIGHSIGNALEN=bool
|
526 |
|
|
TXLOOPFILT=
|
527 |
|
|
TXOUTCLK1_USE_SYNC=bool
|
528 |
|
|
TXOUTDIV2SEL=
|
529 |
|
|
TXPD=bool
|
530 |
|
|
TXPHASESEL=bool
|
531 |
|
|
TXPLLNDIVSEL=
|
532 |
|
|
;TXPOST_PRDRV_DAC= ;3 elems bit_vector
|
533 |
|
|
;TXPOST_TAP_DAC= ;5 elems bit_vector
|
534 |
|
|
TXPOST_TAP_PD=bool
|
535 |
|
|
;TXPRE_PRDRV_DAC= ;3 elems bit_vector
|
536 |
|
|
;TXPRE_TAP_DAC= ;5 elems bit_vector
|
537 |
|
|
TXPRE_TAP_PD=bool
|
538 |
|
|
TXSLEWRATE=bool
|
539 |
|
|
TXTERMTRIM=
|
540 |
|
|
TX_BUFFER_USE=bool
|
541 |
|
|
;TX_CLOCK_DIVIDER= ;2 elems bit_vector
|
542 |
|
|
;VCODAC_INIT= ;10 elems bit_vector
|
543 |
|
|
VCO_CTRL_ENABLE=bool
|
544 |
|
|
|
545 |
|
|
|
546 |
|
|
;added for virtex5 library
|
547 |
|
|
A_INPUT=
|
548 |
|
|
ACASCREG=integer
|
549 |
|
|
ALUMODEREG=integer
|
550 |
|
|
AUTORESET_PATTERN_DETEC=boolean
|
551 |
|
|
AUTORESET_PATTERN_DETECT_OPTINV=
|
552 |
|
|
BANDWIDTH=
|
553 |
|
|
BCASCREG=integer
|
554 |
|
|
CLKFBOUT_MULT=integer
|
555 |
|
|
CLKFBOUT_PHASE=real
|
556 |
|
|
CLKIN1_PERIOD=real
|
557 |
|
|
CLKIN2_PERIOD=real
|
558 |
|
|
CLKOUT0_DIVIDE=integer
|
559 |
|
|
CLKOUT0_DUTY_CYCLE=real
|
560 |
|
|
CLKOUT0_PHASE=real
|
561 |
|
|
CLKOUT1_DIVIDE=integer
|
562 |
|
|
CLKOUT1_DUTY_CYCLE=real
|
563 |
|
|
CLKOUT1_PHASE=real
|
564 |
|
|
CLKOUT2_DIVIDE=integer
|
565 |
|
|
CLKOUT2_DUTY_CYCLE=real
|
566 |
|
|
CLKOUT2_PHASE=real
|
567 |
|
|
CLKOUT3_DIVIDE=integer
|
568 |
|
|
CLKOUT3_DUTY_CYCLE=real
|
569 |
|
|
CLKOUT3_PHASE=real
|
570 |
|
|
CLKOUT4_DIVIDE=integer
|
571 |
|
|
CLKOUT4_DUTY_CYCLE=real
|
572 |
|
|
CLKOUT4_PHASE=real
|
573 |
|
|
CLKOUT5_DIVIDE=integer
|
574 |
|
|
CLKOUT5_DUTY_CYCLE=real
|
575 |
|
|
CLKOUT5_PHASE=real
|
576 |
|
|
COMPENSATION=
|
577 |
|
|
CRC_INIT=
|
578 |
|
|
DELAY_SRC=
|
579 |
|
|
DIVCLK_DIVIDE=integer
|
580 |
|
|
DO_REG=integer
|
581 |
|
|
EN_ECC_READ=boolean
|
582 |
|
|
EN_ECC_SCRUB=boolean
|
583 |
|
|
EN_ECC_WRITE=boolean
|
584 |
|
|
EN_SYN=boolean
|
585 |
|
|
IDELAY_TYPE=
|
586 |
|
|
IDELAY_VALUE=integer
|
587 |
|
|
INIT_70=
|
588 |
|
|
INIT_71=
|
589 |
|
|
INIT_72=
|
590 |
|
|
INIT_73=
|
591 |
|
|
INIT_74=
|
592 |
|
|
INIT_75=
|
593 |
|
|
INIT_76=
|
594 |
|
|
INIT_77=
|
595 |
|
|
INIT_78=
|
596 |
|
|
INIT_79=
|
597 |
|
|
INIT_7A=
|
598 |
|
|
INIT_7B=
|
599 |
|
|
INIT_7C=
|
600 |
|
|
INIT_7D=
|
601 |
|
|
INIT_7E=
|
602 |
|
|
INIT_7F=
|
603 |
|
|
INIT_C=
|
604 |
|
|
INIT_D=
|
605 |
|
|
INITP_08=
|
606 |
|
|
INITP_09=
|
607 |
|
|
INITP_0A=
|
608 |
|
|
INITP_0B=
|
609 |
|
|
INITP_0C=
|
610 |
|
|
INITP_0D=
|
611 |
|
|
INITP_0E=
|
612 |
|
|
INITP_0F=
|
613 |
|
|
MASK=
|
614 |
|
|
MULTCARRYINREG=integer
|
615 |
|
|
ODELAY_VALUE=integer
|
616 |
|
|
PATTERN=
|
617 |
|
|
PLL_PMCD_MODE=boolean
|
618 |
|
|
POLYNOMIAL=
|
619 |
|
|
REF_JITTER=real
|
620 |
|
|
RESET_ON_LOSS_OF_LOCK=boolean
|
621 |
|
|
SEL_MASK=
|
622 |
|
|
SEL_PATTERN=
|
623 |
|
|
SEL_ROUNDING_MASK=
|
624 |
|
|
USE_MULT=
|
625 |
|
|
USE_PATTERN_DETECT=
|
626 |
|
|
USE_SIMD=
|
627 |
|
|
;end of virtex5
|
628 |
|
|
|
629 |
|
|
;added for virtex5 (ise9.1i sp2)
|
630 |
|
|
CLKFBOUT_DESKEW_ADJUST=
|
631 |
|
|
CLKOUT0_DESKEW_ADJUST=
|
632 |
|
|
CLKOUT1_DESKEW_ADJUST=
|
633 |
|
|
CLKOUT2_DESKEW_ADJUST=
|
634 |
|
|
CLKOUT3_DESKEW_ADJUST=
|
635 |
|
|
CLKOUT4_DESKEW_ADJUST=
|
636 |
|
|
CLKOUT5_DESKEW_ADJUST=
|
637 |
|
|
;end of virtex5 (ise9.1i sp2)
|
638 |
|
|
|
639 |
|
|
;added for virtex5 (ise9.2i sp1)
|
640 |
|
|
PCS_COM_CFG=
|
641 |
|
|
SIGNAL_PATTERN=
|
642 |
|
|
INIT_FILE=
|
643 |
|
|
;end of virtex5 (ise9.2i sp1)
|
644 |
|
|
|
645 |
|
|
;added for virtex5 (ise 10.1i)
|
646 |
|
|
SIM_MODE=
|
647 |
|
|
;end
|
648 |
|
|
|
649 |
|
|
;added for spartan6, virtex6 (ise 11.2)
|
650 |
|
|
A0REG=integer
|
651 |
|
|
A1REG=integer
|
652 |
|
|
AC_CAP_DIS_0=boolean
|
653 |
|
|
AC_CAP_DIS_1=boolean
|
654 |
|
|
ADREG=integer
|
655 |
|
|
AUTORESET_PATDET=
|
656 |
|
|
B0REG=integer
|
657 |
|
|
B1REG=integer
|
658 |
|
|
BUFFER_TYPE=
|
659 |
|
|
BYPASS_GCLK_FF=boolean
|
660 |
|
|
CARRYINSEL=
|
661 |
|
|
CARRYOUTREG=integer
|
662 |
|
|
CHAN_BOND_2_MAX_SKEW_0=integer
|
663 |
|
|
CINVCTRL_SEL=boolean
|
664 |
|
|
CLK_SEL_TYPE=
|
665 |
|
|
CLKCM_CFG=boolean
|
666 |
|
|
CLKFBOUT_MULT_F=real
|
667 |
|
|
CLKFXDV_DIVIDE=integer
|
668 |
|
|
CLKFX_MD_MAX=real
|
669 |
|
|
CLKFBOUT_USE_FINE_PS=boolean
|
670 |
|
|
CLKOUT0_DIVIDE_F=real
|
671 |
|
|
CLKOUT0_USE_FINE_PS=boolean
|
672 |
|
|
CLKOUT1_USE_FINE_PS=boolean
|
673 |
|
|
CLKOUT2_USE_FINE_PS=boolean
|
674 |
|
|
CLKOUT3_USE_FINE_PS=boolean
|
675 |
|
|
CLKOUT4_CASCADE=boolean
|
676 |
|
|
CLKOUT4_USE_FINE_PS=boolean
|
677 |
|
|
CLKOUT5_USE_FINE_PS=boolean
|
678 |
|
|
CLKOUT6_DIVIDE=integer
|
679 |
|
|
CLKOUT6_DUTY_CYCLE=real
|
680 |
|
|
CLKOUT6_PHASE=real
|
681 |
|
|
CLKOUT6_USE_FINE_PS=boolean
|
682 |
|
|
CLKRCV_TRST=boolean
|
683 |
|
|
CLOCK_HOLD=boolean
|
684 |
|
|
COUNTER_WRAPAROUND=
|
685 |
|
|
DATA_RATE_OT=
|
686 |
|
|
DDR3_DATA=integer
|
687 |
|
|
DISABLE_JTAG=boolean
|
688 |
|
|
DIVIDE_BYPASS=boolean
|
689 |
|
|
DIVIDE=integer
|
690 |
|
|
DFS_BANDWIDTH=
|
691 |
|
|
DQSMASK_ENABLE=boolean
|
692 |
|
|
DYN_CLK_INV_EN=boolean
|
693 |
|
|
DYN_CLKDIV_INV_EN=boolean
|
694 |
|
|
EN_RSTRAM_A=boolean
|
695 |
|
|
EN_RSTRAM_B=boolean
|
696 |
|
|
FARSRC=
|
697 |
|
|
HIGH_PERFORMANCE_MODE=boolean
|
698 |
|
|
I_INVERT=boolean
|
699 |
|
|
IBUF_DELAY_VALUE=
|
700 |
|
|
IBUF_LOW_PWR=boolean
|
701 |
|
|
IDELAY2_VALUE=integer
|
702 |
|
|
IDELAY_MODE=
|
703 |
|
|
IFD_DELAY_VALUE=
|
704 |
|
|
ISERDESE1 INIT_Q1=integer
|
705 |
|
|
ISERDESE1 INIT_Q2=integer
|
706 |
|
|
ISERDESE1 INIT_Q3=integer
|
707 |
|
|
ISERDESE1 INIT_Q4=integer
|
708 |
|
|
OSERDESE1 INIT_OQ=integer
|
709 |
|
|
OSERDESE1 INIT_TQ=integer
|
710 |
|
|
INMODEREG=integer
|
711 |
|
|
InstancePath=
|
712 |
|
|
ODELAY_TYPE=
|
713 |
|
|
OFB_USED=boolean
|
714 |
|
|
ONESHOT=boolean
|
715 |
|
|
OUTPUT_MODE=
|
716 |
|
|
PROG_MD_BANDWIDTH=
|
717 |
|
|
PROG_USR=boolean
|
718 |
|
|
RAM_MODE=
|
719 |
|
|
REF_JITTER1=real
|
720 |
|
|
REF_JITTER2=real
|
721 |
|
|
REFCLK_FREQUENCY=real
|
722 |
|
|
;REFCLKOUT_DLY= ;10 elems bit_vector
|
723 |
|
|
RST_PRIORITY_A=
|
724 |
|
|
RST_PRIORITY_B=
|
725 |
|
|
RSTREG_PRIORITY_A=
|
726 |
|
|
RSTREG_PRIORITY_B=
|
727 |
|
|
RSTTYPE=
|
728 |
|
|
SETUP_ALL=
|
729 |
|
|
SIM_DEVICE=
|
730 |
|
|
SIM_EFUSE_VALUE=
|
731 |
|
|
SIM_TAPDELAY_VALUE=integer
|
732 |
|
|
SPREAD_SPECTRUM=
|
733 |
|
|
ISERDESE1 SRVAL_Q1=integer
|
734 |
|
|
ISERDESE1 SRVAL_Q2=integer
|
735 |
|
|
ISERDESE1 SRVAL_Q3=integer
|
736 |
|
|
ISERDESE1 SRVAL_Q4=integer
|
737 |
|
|
OSERDESE1 SRVAL_OQ=integer
|
738 |
|
|
OSERDESE1 SRVAL_TQ=integer
|
739 |
|
|
TRAIN_PATTERN=integer
|
740 |
|
|
USE_DOUBLER=boolean
|
741 |
|
|
USE_DPORT=boolean
|
742 |
|
|
;end of spartan6, virtex6 (ise 11.2)
|
743 |
|
|
|
744 |
|
|
; added for virtex6 (ise 11.3)
|
745 |
|
|
TX_PMADATA_OPT=integer
|
746 |
|
|
ENABLE_SYNC=bool
|
747 |
|
|
;end of virtex6 (ise 11.3)
|
748 |
|
|
|
749 |
|
|
[$LIBMAP$]
|
750 |
|
|
work=.
|
751 |
|
|
xilinx=xabelsim
|
752 |
|
|
xilinxun=
|
753 |
|
|
simprims=simprim
|
754 |
|
|
DESIGNS=
|
755 |
|
|
|
756 |
|
|
;FPGA Express
|
757 |
|
|
VIRTEXE=VIRTEX
|
758 |
|
|
COOLRUNNER=XC9500
|
759 |
|
|
COOLRUNNER2=COOLRUNNERII
|
760 |
|
|
SPARTAN2E=SPARTAN2E
|
761 |
|
|
SPARTAN3=SPARTAN3
|
762 |
|
|
SPARTAN3A=SPARTAN3A
|
763 |
|
|
SPARTAN3E=SPARTAN3E
|
764 |
|
|
SPARTANXL=SPARTANX
|
765 |
|
|
XC3000A=XC3000
|
766 |
|
|
XC3000L=XC3000
|
767 |
|
|
XC3100A=XC3000
|
768 |
|
|
XC3100L=XC3000
|
769 |
|
|
XC4000EX=XC4000X
|
770 |
|
|
XC4000L=XC4000E
|
771 |
|
|
XC4000XL=XC4000X
|
772 |
|
|
XC4000XLA=XC4000X
|
773 |
|
|
XC4000XV=XC4000X
|
774 |
|
|
XC9500XL=XC9500
|
775 |
|
|
XC9500XV=XC9500
|
776 |
|
|
|
777 |
|
|
;Synplify
|
778 |
|
|
COOLRUNNERII=COOLRUNNERII
|
779 |
|
|
Unilib=unisim
|
780 |
|
|
XC4000=unisim
|
781 |
|
|
XC5000=unisim
|
782 |
|
|
|
783 |
|
|
;Exemplar
|
784 |
|
|
xcv=unisim
|
785 |
|
|
xcv2=unisim
|
786 |
|
|
xcv2p=unisim
|
787 |
|
|
xcve=unisim
|
788 |
|
|
xi3=unisim
|
789 |
|
|
xi31=unisim
|
790 |
|
|
xi31a=unisim
|
791 |
|
|
xi3a=unisim
|
792 |
|
|
xi3l=unisim
|
793 |
|
|
xi3t=unisim
|
794 |
|
|
xi4=unisim
|
795 |
|
|
xi4a=unisim
|
796 |
|
|
xi4e=unisim
|
797 |
|
|
xi4et=unisim
|
798 |
|
|
xi4ex=unisim
|
799 |
|
|
xi4h=unisim
|
800 |
|
|
xi4l=unisim
|
801 |
|
|
xi4t=unisim
|
802 |
|
|
xi4xl=unisim
|
803 |
|
|
xi4xla=unisim
|
804 |
|
|
xi4xv=unisim
|
805 |
|
|
xi5=unisim
|
806 |
|
|
xi5t=unisim
|
807 |
|
|
xi72a=unisim
|
808 |
|
|
xi73=unisim
|
809 |
|
|
xi7t=unisim
|
810 |
|
|
xi95=unisim
|
811 |
|
|
xi95xl=unisim
|
812 |
|
|
xi95xv=unisim
|
813 |
|
|
xis=unisim
|
814 |
|
|
xis2=unisim
|
815 |
|
|
xis2e=unisim
|
816 |
|
|
xis3=unisim
|
817 |
|
|
xisxl=unisim
|
818 |
|
|
Active_lib=
|
819 |
|
|
UnlinkedDesignLibrary=
|
820 |
|
|
|
821 |
|
|
[$GSRGTS$]
|
822 |
|
|
GSR=
|
823 |
|
|
GR=
|
824 |
|
|
GTS=
|
825 |
|
|
PRLD=
|
826 |
|
|
|
827 |
|
|
[$INCLUDE$]
|
828 |
|
|
line1=library IEEE;
|
829 |
|
|
line2=use IEEE.std_logic_1164.all;
|
830 |
|
|
line3=library UNISIM;
|
831 |
|
|
line4=use UNISIM.vcomponents.all;
|
832 |
|
|
line5=library SIMPRIM;
|
833 |
|
|
line6=use SIMPRIM.vcomponents.all;
|
834 |
|
|
|
835 |
|
|
[TBUF]
|
836 |
|
|
.=BUFT
|
837 |
|
|
|
838 |
|
|
[VCC]
|
839 |
|
|
VCC=P
|
840 |
|
|
|
841 |
|
|
[GND]
|
842 |
|
|
ground=G
|
843 |
|
|
|
844 |
|
|
[X_FF]
|
845 |
|
|
IN=I
|
846 |
|
|
OUT=O
|
847 |
|
|
|
848 |
|
|
;[OPAD]
|
849 |
|
|
;OPAD=I
|
850 |
|
|
;PAD=I
|
851 |
|
|
|
852 |
|
|
;[IPAD]
|
853 |
|
|
;IPAD=I
|
854 |
|
|
;PAD=I
|
855 |
|
|
|
856 |
|
|
;[IOPAD]
|
857 |
|
|
;IOPAD=I
|
858 |
|
|
;PAD=I
|
859 |
|
|
|
860 |
|
|
[X_PU]
|
861 |
|
|
OUT=O
|
862 |
|
|
|
863 |
|
|
[X_LATCH]
|
864 |
|
|
IN=I
|
865 |
|
|
OUT=O
|
866 |
|
|
|
867 |
|
|
[X_LATCHE]
|
868 |
|
|
IN=I
|
869 |
|
|
OUT=O
|
870 |
|
|
|
871 |
|
|
[x_tri]
|
872 |
|
|
IN=I
|
873 |
|
|
OUT=O
|
874 |
|
|
|
875 |
|
|
[x_buf]
|
876 |
|
|
IN=I
|
877 |
|
|
OUT=O
|
878 |
|
|
|
879 |
|
|
[x_zero]
|
880 |
|
|
OUT=O
|
881 |
|
|
[x_one]
|
882 |
|
|
OUT=O
|
883 |
|
|
|
884 |
|
|
[x_and2]
|
885 |
|
|
OUT=O
|
886 |
|
|
IN1=I1
|
887 |
|
|
IN0=I0
|
888 |
|
|
|
889 |
|
|
[x_inv]
|
890 |
|
|
IN=I
|
891 |
|
|
OUT=O
|
892 |
|
|
|
893 |
|
|
[x_or2]
|
894 |
|
|
IN0=I0
|
895 |
|
|
IN1=I1
|
896 |
|
|
OUT=O
|
897 |
|
|
|
898 |
|
|
[x_ckbuf]
|
899 |
|
|
IN=I
|
900 |
|
|
OUT=O
|
901 |
|
|
|
902 |
|
|
[x_and3]
|
903 |
|
|
IN0=I0
|
904 |
|
|
IN1=I1
|
905 |
|
|
IN2=I2
|
906 |
|
|
OUT=O
|
907 |
|
|
|
908 |
|
|
[x_and4]
|
909 |
|
|
IN0=I0
|
910 |
|
|
IN1=I1
|
911 |
|
|
IN2=I2
|
912 |
|
|
IN3=I3
|
913 |
|
|
OUT=O
|
914 |
|
|
|
915 |
|
|
[x_and5]
|
916 |
|
|
IN0=I0
|
917 |
|
|
IN1=I1
|
918 |
|
|
IN2=I2
|
919 |
|
|
IN3=I3
|
920 |
|
|
IN4=I4
|
921 |
|
|
OUT=O
|
922 |
|
|
|
923 |
|
|
[x_and6]
|
924 |
|
|
IN0=I0
|
925 |
|
|
IN1=I1
|
926 |
|
|
IN2=I2
|
927 |
|
|
IN3=I3
|
928 |
|
|
IN4=I4
|
929 |
|
|
IN5=I5
|
930 |
|
|
OUT=O
|
931 |
|
|
|
932 |
|
|
[x_and7]
|
933 |
|
|
IN0=I0
|
934 |
|
|
IN1=I1
|
935 |
|
|
IN2=I2
|
936 |
|
|
IN3=I3
|
937 |
|
|
IN4=I4
|
938 |
|
|
IN5=I5
|
939 |
|
|
IN6=I6
|
940 |
|
|
OUT=O
|
941 |
|
|
|
942 |
|
|
[x_and8]
|
943 |
|
|
IN0=I0
|
944 |
|
|
IN1=I1
|
945 |
|
|
IN2=I2
|
946 |
|
|
IN3=I3
|
947 |
|
|
IN4=I4
|
948 |
|
|
IN5=I5
|
949 |
|
|
IN6=I6
|
950 |
|
|
IN7=I7
|
951 |
|
|
OUT=O
|
952 |
|
|
|
953 |
|
|
[x_and16]
|
954 |
|
|
IN0=I0
|
955 |
|
|
IN1=I1
|
956 |
|
|
IN2=I2
|
957 |
|
|
IN3=I3
|
958 |
|
|
IN4=I4
|
959 |
|
|
IN5=I5
|
960 |
|
|
IN6=I6
|
961 |
|
|
IN7=I7
|
962 |
|
|
IN8=I8
|
963 |
|
|
IN9=I9
|
964 |
|
|
IN10=I10
|
965 |
|
|
IN11=I11
|
966 |
|
|
IN12=I12
|
967 |
|
|
IN13=I13
|
968 |
|
|
IN14=I14
|
969 |
|
|
IN15=I15
|
970 |
|
|
OUT=O
|
971 |
|
|
|
972 |
|
|
[x_or2]
|
973 |
|
|
IN0=I0
|
974 |
|
|
IN1=I1
|
975 |
|
|
OUT=O
|
976 |
|
|
|
977 |
|
|
[x_or3]
|
978 |
|
|
IN0=I0
|
979 |
|
|
IN1=I1
|
980 |
|
|
IN2=I2
|
981 |
|
|
OUT=O
|
982 |
|
|
|
983 |
|
|
[x_or4]
|
984 |
|
|
IN0=I0
|
985 |
|
|
IN1=I1
|
986 |
|
|
IN2=I2
|
987 |
|
|
IN3=I3
|
988 |
|
|
OUT=O
|
989 |
|
|
|
990 |
|
|
[x_or5]
|
991 |
|
|
IN0=I0
|
992 |
|
|
IN1=I1
|
993 |
|
|
IN2=I2
|
994 |
|
|
IN3=I3
|
995 |
|
|
IN4=I4
|
996 |
|
|
OUT=O
|
997 |
|
|
|
998 |
|
|
[x_or6]
|
999 |
|
|
IN0=I0
|
1000 |
|
|
IN1=I1
|
1001 |
|
|
IN2=I2
|
1002 |
|
|
IN3=I3
|
1003 |
|
|
IN4=I4
|
1004 |
|
|
IN5=I5
|
1005 |
|
|
OUT=O
|
1006 |
|
|
|
1007 |
|
|
[x_or7]
|
1008 |
|
|
IN0=I0
|
1009 |
|
|
IN1=I1
|
1010 |
|
|
IN2=I2
|
1011 |
|
|
IN3=I3
|
1012 |
|
|
IN4=I4
|
1013 |
|
|
IN5=I5
|
1014 |
|
|
IN6=I6
|
1015 |
|
|
OUT=O
|
1016 |
|
|
|
1017 |
|
|
|
1018 |
|
|
[x_or8]
|
1019 |
|
|
IN0=I0
|
1020 |
|
|
IN1=I1
|
1021 |
|
|
IN2=I2
|
1022 |
|
|
IN3=I3
|
1023 |
|
|
IN4=I4
|
1024 |
|
|
IN5=I5
|
1025 |
|
|
IN6=I6
|
1026 |
|
|
IN7=I7
|
1027 |
|
|
OUT=O
|
1028 |
|
|
|
1029 |
|
|
[x_or16]
|
1030 |
|
|
IN0=I0
|
1031 |
|
|
IN1=I1
|
1032 |
|
|
IN2=I2
|
1033 |
|
|
IN3=I3
|
1034 |
|
|
IN4=I4
|
1035 |
|
|
IN5=I5
|
1036 |
|
|
IN6=I6
|
1037 |
|
|
IN7=I7
|
1038 |
|
|
IN8=I8
|
1039 |
|
|
IN9=I9
|
1040 |
|
|
IN10=I10
|
1041 |
|
|
IN11=I11
|
1042 |
|
|
IN12=I12
|
1043 |
|
|
IN13=I13
|
1044 |
|
|
IN14=I14
|
1045 |
|
|
IN15=I15
|
1046 |
|
|
OUT=O
|
1047 |
|
|
|
1048 |
|
|
[x_xor2]
|
1049 |
|
|
IN0=I0
|
1050 |
|
|
IN1=I1
|
1051 |
|
|
IN2=I2
|
1052 |
|
|
OUT=O
|
1053 |
|
|
|
1054 |
|
|
[x_xor3]
|
1055 |
|
|
IN0=I0
|
1056 |
|
|
IN1=I1
|
1057 |
|
|
IN2=I2
|
1058 |
|
|
OUT=O
|
1059 |
|
|
|
1060 |
|
|
[x_xor4]
|
1061 |
|
|
IN0=I0
|
1062 |
|
|
IN1=I1
|
1063 |
|
|
IN2=I2
|
1064 |
|
|
IN3=I3
|
1065 |
|
|
OUT=O
|
1066 |
|
|
|
1067 |
|
|
[x_xor5]
|
1068 |
|
|
IN0=I0
|
1069 |
|
|
IN1=I1
|
1070 |
|
|
IN2=I2
|
1071 |
|
|
IN3=I3
|
1072 |
|
|
IN4=I4
|
1073 |
|
|
OUT=O
|
1074 |
|
|
|
1075 |
|
|
|
1076 |
|
|
[x_lut2]
|
1077 |
|
|
OUT=O
|
1078 |
|
|
|
1079 |
|
|
[x_lut3]
|
1080 |
|
|
OUT=O
|
1081 |
|
|
|
1082 |
|
|
[x_lut4]
|
1083 |
|
|
OUT=O
|
1084 |
|
|
|
1085 |
|
|
[x_RAM16]
|
1086 |
|
|
OUT=O
|
1087 |
|
|
IN=I
|
1088 |
|
|
|
1089 |
|
|
[x_RAM32]
|
1090 |
|
|
OUT=O
|
1091 |
|
|
IN=I
|
1092 |
|
|
|
1093 |
|
|
[x_RAMS16]
|
1094 |
|
|
OUT=O
|
1095 |
|
|
IN=I
|
1096 |
|
|
|
1097 |
|
|
[x_RAMS32]
|
1098 |
|
|
OUT=O
|
1099 |
|
|
IN=I
|
1100 |
|
|
|
1101 |
|
|
[x_RAMD16]
|
1102 |
|
|
OUT=O
|
1103 |
|
|
IN=I
|
1104 |
|
|
|
1105 |
|
|
[x_RAMD32]
|
1106 |
|
|
OUT=O
|
1107 |
|
|
IN=I
|
1108 |
|
|
|
1109 |
|
|
[x_MUX2]
|
1110 |
|
|
OUT=O
|
1111 |
|
|
INA=IA
|
1112 |
|
|
INB=IB
|
1113 |
|
|
|
1114 |
|
|
[x_OR32]
|
1115 |
|
|
IN0=I0
|
1116 |
|
|
IN1=I1
|
1117 |
|
|
IN2=I2
|
1118 |
|
|
IN3=I3
|
1119 |
|
|
IN4=I4
|
1120 |
|
|
IN5=I5
|
1121 |
|
|
IN6=I6
|
1122 |
|
|
IN7=I7
|
1123 |
|
|
IN8=I8
|
1124 |
|
|
IN9=I9
|
1125 |
|
|
IN10=I10
|
1126 |
|
|
IN11=I11
|
1127 |
|
|
IN12=I12
|
1128 |
|
|
IN13=I13
|
1129 |
|
|
IN14=I14
|
1130 |
|
|
IN15=I15
|
1131 |
|
|
IN16=I16
|
1132 |
|
|
IN17=I17
|
1133 |
|
|
IN18=I18
|
1134 |
|
|
IN19=I19
|
1135 |
|
|
IN20=I20
|
1136 |
|
|
IN21=I21
|
1137 |
|
|
IN22=I22
|
1138 |
|
|
IN23=I23
|
1139 |
|
|
IN24=I24
|
1140 |
|
|
IN25=I25
|
1141 |
|
|
IN26=I26
|
1142 |
|
|
IN27=I27
|
1143 |
|
|
IN28=I28
|
1144 |
|
|
IN29=I29
|
1145 |
|
|
IN30=I30
|
1146 |
|
|
IN31=I31
|
1147 |
|
|
OUT=O
|
1148 |
|
|
|
1149 |
|
|
[x_PD]
|
1150 |
|
|
OUT=O
|
1151 |
|
|
|
1152 |
|
|
[x_XOR16]
|
1153 |
|
|
IN0=I0
|
1154 |
|
|
IN1=I1
|
1155 |
|
|
IN2=I2
|
1156 |
|
|
IN3=I3
|
1157 |
|
|
IN4=I4
|
1158 |
|
|
IN5=I5
|
1159 |
|
|
IN6=I6
|
1160 |
|
|
IN7=I7
|
1161 |
|
|
IN8=I8
|
1162 |
|
|
IN9=I9
|
1163 |
|
|
IN10=I10
|
1164 |
|
|
IN11=I11
|
1165 |
|
|
IN12=I12
|
1166 |
|
|
IN13=I13
|
1167 |
|
|
IN14=I14
|
1168 |
|
|
IN15=I15
|
1169 |
|
|
OUT=O
|
1170 |
|
|
|
1171 |
|
|
[x_XOR32]
|
1172 |
|
|
IN0=I0
|
1173 |
|
|
IN1=I1
|
1174 |
|
|
IN2=I2
|
1175 |
|
|
IN3=I3
|
1176 |
|
|
IN4=I4
|
1177 |
|
|
IN5=I5
|
1178 |
|
|
IN6=I6
|
1179 |
|
|
IN7=I7
|
1180 |
|
|
IN8=I8
|
1181 |
|
|
IN9=I9
|
1182 |
|
|
IN10=I10
|
1183 |
|
|
IN11=I11
|
1184 |
|
|
IN12=I12
|
1185 |
|
|
IN13=I13
|
1186 |
|
|
IN14=I14
|
1187 |
|
|
IN15=I15
|
1188 |
|
|
IN16=I16
|
1189 |
|
|
IN17=I17
|
1190 |
|
|
IN18=I18
|
1191 |
|
|
IN19=I19
|
1192 |
|
|
IN20=I20
|
1193 |
|
|
IN21=I21
|
1194 |
|
|
IN22=I22
|
1195 |
|
|
IN23=I23
|
1196 |
|
|
IN24=I24
|
1197 |
|
|
IN25=I25
|
1198 |
|
|
IN26=I26
|
1199 |
|
|
IN27=I27
|
1200 |
|
|
IN28=I28
|
1201 |
|
|
IN29=I29
|
1202 |
|
|
IN30=I30
|
1203 |
|
|
IN31=I31
|
1204 |
|
|
OUT=O
|
1205 |
|
|
|
1206 |
|
|
[x_AND32]
|
1207 |
|
|
IN0=I0
|
1208 |
|
|
IN1=I1
|
1209 |
|
|
IN2=I2
|
1210 |
|
|
IN3=I3
|
1211 |
|
|
IN4=I4
|
1212 |
|
|
IN5=I5
|
1213 |
|
|
IN6=I6
|
1214 |
|
|
IN7=I7
|
1215 |
|
|
IN8=I8
|
1216 |
|
|
IN9=I9
|
1217 |
|
|
IN10=I10
|
1218 |
|
|
IN11=I11
|
1219 |
|
|
IN12=I12
|
1220 |
|
|
IN13=I13
|
1221 |
|
|
IN14=I14
|
1222 |
|
|
IN15=I15
|
1223 |
|
|
IN16=I16
|
1224 |
|
|
IN17=I17
|
1225 |
|
|
IN18=I18
|
1226 |
|
|
IN19=I19
|
1227 |
|
|
IN20=I20
|
1228 |
|
|
IN21=I21
|
1229 |
|
|
IN22=I22
|
1230 |
|
|
IN23=I23
|
1231 |
|
|
IN24=I24
|
1232 |
|
|
IN25=I25
|
1233 |
|
|
IN26=I26
|
1234 |
|
|
IN27=I27
|
1235 |
|
|
IN28=I28
|
1236 |
|
|
IN29=I29
|
1237 |
|
|
IN30=I30
|
1238 |
|
|
IN31=I31
|
1239 |
|
|
OUT=O
|
1240 |
|
|
|
1241 |
|
|
[x_XOR6]
|
1242 |
|
|
IN0=I0
|
1243 |
|
|
IN1=I1
|
1244 |
|
|
IN2=I2
|
1245 |
|
|
IN3=I3
|
1246 |
|
|
IN4=I4
|
1247 |
|
|
IN5=I5
|
1248 |
|
|
OUT=O
|
1249 |
|
|
|
1250 |
|
|
[x_XOR7]
|
1251 |
|
|
IN0=I0
|
1252 |
|
|
IN1=I1
|
1253 |
|
|
IN2=I2
|
1254 |
|
|
IN3=I3
|
1255 |
|
|
IN4=I4
|
1256 |
|
|
IN5=I5
|
1257 |
|
|
IN6=I6
|
1258 |
|
|
OUT=O
|
1259 |
|
|
|
1260 |
|
|
[x_XOR8]
|
1261 |
|
|
IN0=I0
|
1262 |
|
|
IN1=I1
|
1263 |
|
|
IN2=I2
|
1264 |
|
|
IN3=I3
|
1265 |
|
|
IN4=I4
|
1266 |
|
|
IN5=I5
|
1267 |
|
|
IN6=I6
|
1268 |
|
|
IN7=I7
|
1269 |
|
|
OUT=O
|
1270 |
|
|
|
1271 |
|
|
[X_SFF]
|
1272 |
|
|
IN=I
|
1273 |
|
|
OUT=O
|
1274 |
|
|
|
1275 |
|
|
[X_SUH]
|
1276 |
|
|
IN=I
|
1277 |
|
|
|
1278 |
|
|
[FDCE]
|
1279 |
|
|
GSR=$HIDDEN$
|
1280 |
|
|
[FDPE]
|
1281 |
|
|
GSR=$HIDDEN$
|
1282 |
|
|
[IFDX]
|
1283 |
|
|
GSR=$HIDDEN$
|
1284 |
|
|
[IFDXI]
|
1285 |
|
|
GSR=$HIDDEN$
|
1286 |
|
|
[ILDX_1]
|
1287 |
|
|
GSR=$HIDDEN$
|
1288 |
|
|
GTS=$HIDDEN$
|
1289 |
|
|
[ILDXI_1]
|
1290 |
|
|
GSR=$HIDDEN$
|
1291 |
|
|
GTS=$HIDDEN$
|
1292 |
|
|
[ILFFX]
|
1293 |
|
|
GSR=$HIDDEN$
|
1294 |
|
|
[ILFFXI]
|
1295 |
|
|
GSR=$HIDDEN$
|
1296 |
|
|
[ILFLX_1]
|
1297 |
|
|
GSR=$HIDDEN$
|
1298 |
|
|
GTS=$HIDDEN$
|
1299 |
|
|
[ILFLXI_1]
|
1300 |
|
|
GSR=$HIDDEN$
|
1301 |
|
|
GTS=$HIDDEN$
|
1302 |
|
|
[LDCE_1]
|
1303 |
|
|
GSR=$HIDDEN$
|
1304 |
|
|
GTS=$HIDDEN$
|
1305 |
|
|
[LDPE]
|
1306 |
|
|
GSR=$HIDDEN$
|
1307 |
|
|
GTS=$HIDDEN$
|
1308 |
|
|
[LDPE_1]
|
1309 |
|
|
GSR=$HIDDEN$
|
1310 |
|
|
GTS=$HIDDEN$
|
1311 |
|
|
[OAND2]
|
1312 |
|
|
GTS=$HIDDEN$
|
1313 |
|
|
[OBUF]
|
1314 |
|
|
GTS=$HIDDEN$
|
1315 |
|
|
[OBUFT]
|
1316 |
|
|
GTS=$HIDDEN$
|
1317 |
|
|
[OFDTX]
|
1318 |
|
|
GSR=$HIDDEN$
|
1319 |
|
|
GTS=$HIDDEN$
|
1320 |
|
|
[OFDTXI]
|
1321 |
|
|
GSR=$HIDDEN$
|
1322 |
|
|
GTS=$HIDDEN$
|
1323 |
|
|
[OFDX]
|
1324 |
|
|
GSR=$HIDDEN$
|
1325 |
|
|
GTS=$HIDDEN$
|
1326 |
|
|
[OFDXI]
|
1327 |
|
|
GTS=$HIDDEN$
|
1328 |
|
|
GSR=$HIDDEN$
|
1329 |
|
|
[OMUX2]
|
1330 |
|
|
GTS=$HIDDEN$
|
1331 |
|
|
[ONAND2]
|
1332 |
|
|
GTS=$HIDDEN$
|
1333 |
|
|
[ONOR2]
|
1334 |
|
|
GTS=$HIDDEN$
|
1335 |
|
|
[OOR2]
|
1336 |
|
|
GTS=$HIDDEN$
|
1337 |
|
|
[OXNOR2]
|
1338 |
|
|
GTS=$HIDDEN$
|
1339 |
|
|
[OXOR2]
|
1340 |
|
|
GTS=$HIDDEN$
|