osmo-sdr/fpga/hw-v2/bde.set @ master
1 | c62f5734 | Christian Daniel | ########## |
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2 | BUS DEFAULT NAME |
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3 | BUS |
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4 | ########## |
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5 | BUS DEFAULT TYPE |
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6 | STD_LOGIC_VECTOR |
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7 | ########## |
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8 | BUS GLOBAL CONNECTOR |
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9 | GlobalBus |
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10 | ########## |
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11 | BUS INDEX END |
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12 | 0 |
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13 | ########## |
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14 | BUS INDEX START |
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15 | 7 |
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16 | ########## |
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17 | BUS TERMINAL BUFFER |
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18 | BusBuffer |
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19 | ########## |
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20 | BUS TERMINAL IN |
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21 | BusInput |
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22 | ########## |
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23 | BUS TERMINAL INOUT |
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24 | BusBidirectional |
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25 | ########## |
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26 | BUS TERMINAL OUT |
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27 | BusOutput |
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28 | ########## |
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29 | CHECK DIAGRAM |
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30 | YES |
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31 | ########## |
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32 | DEFAULT BDE LANGUAGE |
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33 | VHDL |
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34 | ########## |
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35 | FILE HEADER |
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36 | -- |
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37 | |||
38 | -- file <GENERATEDFILE> |
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39 | |||
40 | -- generated <TIME> |
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41 | |||
42 | -- from <SOURCEFILE> |
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43 | |||
44 | -- by <GENERATORVERSION> |
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45 | |||
46 | -- |
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47 | ########## |
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48 | GLOBAL CONNECTOR |
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49 | Global |
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50 | ########## |
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51 | GND DEFAULT TYPE |
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52 | STD_LOGIC |
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53 | ########## |
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54 | GND DEFAULT VALUE |
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55 | '0' |
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56 | ########## |
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57 | HANGING WIRE DEFAULT TYPE |
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58 | STD_LOGIC |
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59 | ########## |
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60 | HANGING WIRE DEFAULT VALUE |
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61 | 'Z' |
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62 | ########## |
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63 | INCLUDE ACTIVE LIBRARY CLAUSE |
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64 | 0 |
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65 | ########## |
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66 | INCREMENT NET FACTOR |
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67 | 1 |
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68 | ########## |
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69 | INCREMENT NET START |
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70 | 0 |
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71 | ########## |
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72 | INCREMENT NETS |
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73 | 0 |
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74 | ########## |
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75 | LIBRARIES |
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76 | library IEEE; |
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77 | |||
78 | use IEEE.std_logic_1164.all; |
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79 | ########## |
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80 | TERMINAL BUFFER |
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81 | Buffer |
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82 | ########## |
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83 | TERMINAL IN |
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84 | Input |
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85 | ########## |
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86 | TERMINAL INOUT |
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87 | Bidirectional |
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88 | ########## |
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89 | TERMINAL OUT |
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90 | Output |
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91 | ########## |
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92 | USE GLOBAL DEFAULTS |
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93 | 1 |
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94 | ########## |
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95 | VCC DEFAULT TYPE |
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96 | STD_LOGIC |
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97 | ########## |
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98 | VCC DEFAULT VALUE |
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99 | '1' |
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100 | ########## |
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101 | VERILOG DANGLING DEFAULT VALUE |
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102 | 1'bZ |
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103 | ########## |
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104 | VERILOG DESIGN UNIT HEADER |
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105 | `timescale 1ps / 1ps |
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106 | ########## |
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107 | VERILOG FILE HEADER |
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108 | // |
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109 | |||
110 | // file <GENERATEDFILE> |
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111 | |||
112 | // generated <TIME> |
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113 | |||
114 | // from <SOURCEFILE> |
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115 | |||
116 | // by <GENERATORVERSION> |
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117 | |||
118 | // |
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119 | ########## |
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120 | VERILOG GND DEFAULT TYPE |
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121 | supply0 |
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122 | ########## |
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123 | VERILOG GND DEFAULT VALUE |
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124 | 1'b0 |
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125 | ########## |
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126 | VERILOG VCC DEFAULT TYPE |
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127 | supply1 |
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128 | ########## |
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129 | VERILOG VCC DEFAULT VALUE |
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130 | 1'b1 |
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131 | ########## |
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132 | WIRE DEFAULT NAME |
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133 | NET |
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134 | ########## |
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135 | WIRE DEFAULT TYPE |
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136 | STD_LOGIC |