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Anonymous, 02/19/2016 10:52 PM
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= Welcome to the UmTRX project Developer Wiki =
Image(UmTRX-scheme_simple-cropped-1024w.jpg,40%)
UmTRX is a dual-channel wide-band SDR transceiver that is designed to be used with [http://wush.net/trac/rangepublic OpenBTS] and [http://openbsc.osmocom.org/trac/wiki/OsmoBTS OsmoBTS] GSM base stations. Given its SDR architecture UmTRX can easily be used with many other RF applications, and a combination of FPGA and FPRF (Field-Programmable RF) technology plus the ability to process data on a CPU or a DSP, makes it an extraordinarily flexible platform.
UmTRX is connected to a host via gigabit Ethernet. The Fairwaves version of UHD provides FPGA HDL and firmware, along with a host driver.
Laboratory packages and turnkey solutions are available from [http://fairwaves.ru/ Fairwaves].
Intro, user info and blogFor a more detailed introduction, user information and the project blog, see [http://umtrx.org]
Developers * Design documentation, UHD sources and datasheets etc. * Altium Designer files, BOM, schematics and layout PDFs: {{{git clone https://github.com/fairwaves/umtrx-schematics.git}}} * Fairwaves version of UHD: {{{git clone https://github.com/fairwaves/UHD-Fairwaves.git}}} * LMS6002D transceiver IC documentation: {{{git clone https://github.com/myriadrf/LMS6002D-docs.git}}} * Mailing list: [http://lists.osmocom.org/cgi-bin/mailman/listinfo/umtrx] * [wiki:MailingListRules Mailing list rules] * Firmware building, flashing and booting * [wiki:Building_firmware Building firmware] * [wiki:FlashingUmTRX Flashing firmware] * [wiki:BootingAndSafeMode Booting and safe mode] * Roadmap * [wiki:UmTRX_Roadmap UmTRX] * [wiki:UHD-Fairwaves_Roadmap UHD-Fairwaves] LicensingAltium Designer schematic and board layout files are made available under the Creative Commons Attribution-!ShareAlike 3.0 Unported license.
FPGA HDL, and firmware and host driver sources are made available under the GPL v3 license.
CommunityUmTRX is an Osmocom project, and also a partner project of [http://myriadrf.org/ Myriad-RF].
Contributors- Alexander Chemeris — project leader
- Andrey Sviyazov — hardware design
- Sergey Kostanbaev — FPGA HDL
- Andrey Sviyazov — initial host-side code
- Sylvain Munaut — various improvements
- Eric Wild — host-side code
- Sergey Kostanbaev — debugging
- Andrey Bakhmat — logo, diagrams and photos
- Andrew Back — community management
Updated by about 8 years ago · 6 revisions