Osmo-e1-xcvr » History » Version 10
laforge, 12/23/2017 01:57 PM
1 | 8 | laforge | {{>toc}} |
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2 | 1 | laforge | |
3 | 8 | laforge | h1. osmo-e1-xcvr |
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6 | 1 | laforge | This is a simple hardware project that aims to generate a reusable module |
7 | for interfacing E1/T1/J1 lines from various custom FPGA/CPLD/microcontroller |
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8 | projects. |
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9 | |||
10 | The board contains tranformers, the analog circuitry, the LIU (line interface |
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11 | unit), an oscillator as well as an integrated transceiver chip. |
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12 | |||
13 | It exposes the control interface (SPI) as well as the decoded synchronous |
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14 | Rx/Tx bitstreams each on a 2x5pin header. |
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15 | |||
16 | Framer, Multiplexe,r HDLC decoder or anything like that is out-of-scope for |
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17 | now. The idea relaly is to provide an interface as low-level as possible. |
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19 | One of the ideas is to create a "soft E1" interface, where the Rx/Tx bitstreams |
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20 | are interfaced with the SSC of an AT91SAM3S and subsequently passed into a PC |
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21 | via USB. The 2Mbps signal is very low-bandwidth, so that a pure software |
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22 | implementation should be absolutely no problem for todays computing power. |
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25 | 8 | laforge | h2. Status |
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28 | 1 | laforge | The project is in design phase. Initial design has finished, but needs to be |
29 | reviewed. First prototype PCBs are evaluated since January 12, 2012 |
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32 | 8 | laforge | h2. Hardware pictures |
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35 | |||
36 | h3. Bare PCB |
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37 | |||
38 | 9 | laforge | !{width:50%}osmo-e1-xcvr-pcb.jpg! |
39 | 7 | laforge | |
40 | 8 | laforge | |
41 | h3. Populated PCB |
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42 | |||
43 | 9 | laforge | !{width:50%}osmo-e1-xcvr.jpg! |
44 | 1 | laforge | |
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46 | 8 | laforge | h2. Hardware Documentation |
47 | 1 | laforge | |
48 | 8 | laforge | h3. JP2: TDM interface |
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51 | 1 | laforge | JP2 contains the serial TDM bitstream + clock for Rx and Tx direction. The signals are |
52 | ||Pin||Name||Description|| |
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53 | ||1||GND||Ground|| |
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54 | ||2||nRST||low-active reset line, uC can reset the transceiver by pulling this low|| |
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55 | ||3||NC|||| |
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56 | ||4||LOS||Loss of Signal|| |
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57 | ||5||TDN||Transmit Data Negative|| |
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58 | ||6||RCLK||Receive Clock|| |
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59 | ||7||TD/TDP||Transmit Data / Transmit Data Positive|| |
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60 | ||8||RD/RDP||Receive Data / Receive Data Positive|| |
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61 | 10 | laforge | ||9||TCLK||Transmitter Clock. Depending on JP9, this is an input into the board, or an output|| |
62 | 1 | laforge | ||10||RDN/CV||Receive Data Negative / Code Violation|| |
63 | |||
64 | 8 | laforge | h3. JP1: SPI control |
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66 | |||
67 | 1 | laforge | This is how the external microcontroller can control the transceiver chip. |
68 | 3 | laforge | |
69 | 1 | laforge | ||Pin||Name||Description|| |
70 | 3 | laforge | ||1||VCC_IN||Vcc input, board can be supplied form here if SJ2 is closed|| |
71 | 1 | laforge | ||2||GND||Ground|| |
72 | ||3||NC||Not connected|| |
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73 | ||4||nINT||low-active interrupt output, when transceiver wants to interrupt uC""|| |
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74 | ||5||NC||Not connected|| |
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75 | ||6||NC||Not connected|| |
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76 | ||7||SDO||Serial Data Out (MISO)|| |
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77 | ||8||SDI||Serial Data In (MOSI)|| |
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78 | ||9||SCLK||Serial Clock|| |
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79 | ||10||nCS||low-active chip-select of the SPI|| |
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80 | |||
81 | |||
82 | 8 | laforge | h3. JP9 |
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84 | |||
85 | 2 | laforge | JP10 switches the master clock (MCLK) of the transceiver between two on-board oscillators |
86 | 1 | laforge | of 2.048 MHz and 1.544 MHz. This is required for selecting between E1 or T1/J1 mode. |
87 | |||
88 | ||1-2||2.048 MHz (E1) mode|| |
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89 | ||2-3||1.544 MHz (T1/J1) mode|| |
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90 | |||
91 | |||
92 | 8 | laforge | h3. JP10 |
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95 | 1 | laforge | This jumper decides if the 2.048/1.544 MHz MCLK should also be used as TDM Transmit Clock. |
96 | |||
97 | ||closed||use MCLK as TCLK source, TCLK pin on JP2 is output|| |
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98 | ||open||external circuit provides TCLK on JP2|| |
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99 | |||
100 | |||
101 | 8 | laforge | h3. JP3 + JP4 |
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103 | |||
104 | 1 | laforge | JP3can be used to supply power to the board. |
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106 | |||
107 | 8 | laforge | h2. show me the code |
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109 | |||
110 | 4 | laforge | http://cgit.osmocom.org/cgit/osmo-e1-xcvr/ |
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112 | 8 | laforge | |
113 | h2. TODO list |
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114 | |||
115 | * hardware |
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116 | ** make ridiculously large test pads smaller |
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117 | ** move C1 closer to U1 VDDIO pad (19) |
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118 | ** remove $ sign from component names |
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119 | ** define which value C5 should use |
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120 | ** mark pin 1 of J1 / J2 on copper + silk screen |
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121 | ** different footprint for L1 ? value ? |
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122 | ** JP10 is a big too close to J1 |
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123 | * software |
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124 | ** implement minimal SPI driver to initialize transceiver chip |