Osmo-e1-xcvr » History » Version 11
laforge, 05/04/2018 11:57 AM
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1 | 8 | laforge | {{>toc}} |
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2 | 1 | laforge | |
3 | 8 | laforge | h1. osmo-e1-xcvr |
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6 | 11 | laforge | This is a simple hardware project that aims to generate a reusable module for interfacing E1/T1/J1 lines from various custom FPGA/CPLD/microcontroller projects. |
7 | 1 | laforge | |
8 | 11 | laforge | The board contains tranformers, the analog circuitry, the LIU (line interface unit), an oscillator as well as an integrated transceiver chip. |
9 | 1 | laforge | |
10 | 11 | laforge | It exposes the control interface (SPI) as well as the decoded synchronous Rx/Tx bitstreams each on a 2x5pin header. |
11 | 1 | laforge | |
12 | 11 | laforge | Framer, Multiplexer, HDLC decoder or anything like that is out-of-scope for now. The idea relaly is to provide an interface as low-level as possible. |
13 | 1 | laforge | |
14 | 11 | laforge | One of the ideas is to create a "soft E1" interface, where the Rx/Tx bitstreams are interfaced with the SSC of an AT91SAM3S and subsequently passed into a PC via USB. The 2Mbps signal is very low-bandwidth, so that a pure software implementation should be absolutely no problem for todays computing power. |
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17 | h2. Status |
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18 | 1 | laforge | |
19 | 11 | laforge | The project is in design phase. Initial design has finished, but needs to be reviewed. First prototype PCBs are evaluated since January 12, 2012 |
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22 | 8 | laforge | h2. Hardware pictures |
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26 | h3. Bare PCB |
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28 | 9 | laforge | !{width:50%}osmo-e1-xcvr-pcb.jpg! |
29 | 7 | laforge | |
30 | 8 | laforge | |
31 | h3. Populated PCB |
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33 | 9 | laforge | !{width:50%}osmo-e1-xcvr.jpg! |
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36 | 8 | laforge | h2. Hardware Documentation |
37 | 1 | laforge | |
38 | 8 | laforge | h3. JP2: TDM interface |
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41 | 1 | laforge | JP2 contains the serial TDM bitstream + clock for Rx and Tx direction. The signals are |
42 | ||Pin||Name||Description|| |
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43 | ||1||GND||Ground|| |
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44 | ||2||nRST||low-active reset line, uC can reset the transceiver by pulling this low|| |
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45 | ||3||NC|||| |
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46 | ||4||LOS||Loss of Signal|| |
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47 | ||5||TDN||Transmit Data Negative|| |
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48 | ||6||RCLK||Receive Clock|| |
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49 | ||7||TD/TDP||Transmit Data / Transmit Data Positive|| |
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50 | ||8||RD/RDP||Receive Data / Receive Data Positive|| |
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51 | 10 | laforge | ||9||TCLK||Transmitter Clock. Depending on JP9, this is an input into the board, or an output|| |
52 | 1 | laforge | ||10||RDN/CV||Receive Data Negative / Code Violation|| |
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54 | 8 | laforge | h3. JP1: SPI control |
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56 | |||
57 | 1 | laforge | This is how the external microcontroller can control the transceiver chip. |
58 | 3 | laforge | |
59 | 1 | laforge | ||Pin||Name||Description|| |
60 | 3 | laforge | ||1||VCC_IN||Vcc input, board can be supplied form here if SJ2 is closed|| |
61 | 1 | laforge | ||2||GND||Ground|| |
62 | ||3||NC||Not connected|| |
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63 | ||4||nINT||low-active interrupt output, when transceiver wants to interrupt uC""|| |
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64 | ||5||NC||Not connected|| |
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65 | ||6||NC||Not connected|| |
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66 | ||7||SDO||Serial Data Out (MISO)|| |
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67 | ||8||SDI||Serial Data In (MOSI)|| |
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68 | ||9||SCLK||Serial Clock|| |
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69 | ||10||nCS||low-active chip-select of the SPI|| |
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72 | 8 | laforge | h3. JP9 |
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75 | 2 | laforge | JP10 switches the master clock (MCLK) of the transceiver between two on-board oscillators |
76 | 1 | laforge | of 2.048 MHz and 1.544 MHz. This is required for selecting between E1 or T1/J1 mode. |
77 | |||
78 | ||1-2||2.048 MHz (E1) mode|| |
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79 | ||2-3||1.544 MHz (T1/J1) mode|| |
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81 | |||
82 | 8 | laforge | h3. JP10 |
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85 | 1 | laforge | This jumper decides if the 2.048/1.544 MHz MCLK should also be used as TDM Transmit Clock. |
86 | |||
87 | ||closed||use MCLK as TCLK source, TCLK pin on JP2 is output|| |
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88 | ||open||external circuit provides TCLK on JP2|| |
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91 | 8 | laforge | h3. JP3 + JP4 |
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94 | 1 | laforge | JP3can be used to supply power to the board. |
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97 | 8 | laforge | h2. show me the code |
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100 | 4 | laforge | http://cgit.osmocom.org/cgit/osmo-e1-xcvr/ |
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102 | 8 | laforge | |
103 | h2. TODO list |
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104 | |||
105 | * hardware |
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106 | ** make ridiculously large test pads smaller |
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107 | ** move C1 closer to U1 VDDIO pad (19) |
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108 | ** remove $ sign from component names |
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109 | ** define which value C5 should use |
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110 | ** mark pin 1 of J1 / J2 on copper + silk screen |
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111 | ** different footprint for L1 ? value ? |
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112 | ** JP10 is a big too close to J1 |
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113 | * software |
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114 | ** implement minimal SPI driver to initialize transceiver chip |