Osmo-e1-xcvr » History » Version 2
laforge, 02/19/2016 10:48 PM
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1 | 1 | laforge | [[PageOutline]] |
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2 | = osmo-e1-xcvr = |
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3 | |||
4 | This is a simple hardware project that aims to generate a reusable module |
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5 | for interfacing E1/T1/J1 lines from various custom FPGA/CPLD/microcontroller |
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6 | projects. |
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7 | |||
8 | The board contains tranformers, the analog circuitry, the LIU (line interface |
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9 | unit), an oscillator as well as an integrated transceiver chip. |
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10 | |||
11 | It exposes the control interface (SPI) as well as the decoded synchronous |
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12 | Rx/Tx bitstreams each on a 2x5pin header. |
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13 | |||
14 | Framer, Multiplexe,r HDLC decoder or anything like that is out-of-scope for |
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15 | now. The idea relaly is to provide an interface as low-level as possible. |
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16 | |||
17 | One of the ideas is to create a "soft E1" interface, where the Rx/Tx bitstreams |
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18 | are interfaced with the SSC of an AT91SAM3S and subsequently passed into a PC |
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19 | via USB. The 2Mbps signal is very low-bandwidth, so that a pure software |
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20 | implementation should be absolutely no problem for todays computing power. |
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21 | |||
22 | == Status == |
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23 | |||
24 | The project is in design phase. Initial design has finished, but needs to be |
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25 | reviewed. First prototype PCBs will be expected in January 2012 |
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26 | |||
27 | == Hardware Documentation == |
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28 | |||
29 | === JP2: TDM interface === |
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30 | |||
31 | JP2 contains the serial TDM bitstream + clock for Rx and Tx direction. The signals are |
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32 | ||Pin||Name||Description|| |
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33 | ||1||GND||Ground|| |
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34 | ||2||nRST||low-active reset line, uC can reset the transceiver by pulling this low|| |
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35 | ||3||NC|||| |
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36 | ||4||LOS||Loss of Signal|| |
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37 | ||5||TDN||Transmit Data Negative|| |
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38 | ||6||RCLK||Receive Clock|| |
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39 | ||7||TD/TDP||Transmit Data / Transmit Data Positive|| |
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40 | ||8||RD/RDP||Receive Data / Receive Data Positive|| |
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41 | ||9||TCLK||Transmitter Clock. Depending on JP9, this is an input into the board, or an output |
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42 | ||10||RDN/CV||Receive Data Negative / Code Violation|| |
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43 | |||
44 | === JP1: SPI control === |
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45 | |||
46 | This is how the external microcontroller can control the transceiver chip. |
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47 | |||
48 | ||Pin||Name||Description|| |
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49 | ||1||GND||Ground|| |
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50 | ||2||NC||Not connected|| |
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51 | ||3||NC||Not connected|| |
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52 | ||4||nINT||low-active interrupt output, when transceiver wants to interrupt uC"" |
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53 | ||5||NC||Not connected|| |
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54 | ||6||nCS||low-active chip-select of the SPI|| |
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55 | ||7||NC||Not connected|| |
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56 | ||8||SDO||Serial Data Out (MISO)|| |
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57 | ||9||SDI||Serial Data In (MOSI)|| |
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58 | ||10||SCLK||Serial Clock|| |
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59 | |||
60 | === JP9 === |
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61 | |||
62 | JP10 switches the master clock (MCLK) of the transceiver between two on-board oscillators |
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63 | of 2.048 MHz and 1.544 MHz. This is required for selecting between E1 or T1/J1 mode. |
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64 | |||
65 | ||1-2||2.048 MHz (E1) mode|| |
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66 | ||2-3||1.544 MHz (T1/J1) mode|| |
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67 | |||
68 | === JP10 === |
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69 | |||
70 | This jumper decides if the 2.048/1.544 MHz MCLK should also be used as TDM Transmit Clock. |
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71 | |||
72 | ||closed||use MCLK as TCLK source, TCLK pin on JP2 is output|| |
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73 | ||open||external circuit provides TCLK on JP2|| |
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74 | |||
75 | === JP3 + JP4 === |
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76 | |||
77 | JP3+JP4 can be used to select which of the pins on the RJ45 connector should be used: |
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78 | |||
79 | They should either all be in setting 1-2, or all be in 2-3, but never mixed. |
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80 | |||
81 | ||1-2||Use pins 3+6 as one pair|| |
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82 | ||2-3||Use pins 1+2 as one pair|| |
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83 | |||
84 | 2 | laforge | === JP5, JP6, JP7, JP8 === |
85 | 1 | laforge | |
86 | Those select between TE mode and NT mode. |
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87 | |||
88 | They should either all be in setting 1-2, or all be in 2-3, but never mixed. |
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89 | |||
90 | == show me the code == |
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91 | |||
92 | http://cgit.osmocom.org/cgit/osmo-e1-xcvr/ |