PageOutline = Integrated Site Controller (CLN1480A) =

This is a unit that interfaces up to 8 Base Radios with the core network of the Dimetra TETRA network (SwMI).

Hardware-wise, it is a PowerPC based system, looking very much like an old-fashioned PC mainboard with both ISA and PCI slots.

The mainboard houses the PowerPC CPU and it has slots for RAM.

There are some extension cards plugged into the system:

• Clock generation card (ISA, full length). * has an integrated GPS receiver, to which you attach a GPS antenna * generates the reference 5MHz clock distributed over Coaxial cable to the Base Radios
• Ethernet Card using DEC tulip chipset (PCI) * This card is what talks to the Base Radios (BR) via 10-Base-2
• Unknown card with RJ-45 jack (REDUND) on the back. Might be E1

There are further inputs and outputs on the system:

• A DB-15 jack for X.21 synchronous serial backhaul (2048Mbps)
• FIXME
• A RS-232 serial port for local configuration

Serial Console === Boot Log === {{{
Copyright Motorola Inc. 1988 - 1996, All Rights Reserved

ACG Debugger/Diagnostics Release Version 1.0 - 06/24/96
COLD Start

Local Memory Found =02000000 (&33554432)

MPU Clock Speed =100Mhz

BUS Clock Speed =67Mhz

Keyboard not connected

Initializing System Memory (DRAM)...

System Memory: 32MB, Parity NOT Enabled (Non-Parity-Memory Detected)
L2Cache: NONE, Parity NOT Enabled

SelfTest/Boots about to Begin... Press <BREAK> at anytime to Abort ALL

ROMBoot about to Begin... Press <ESC> to Bypass, <SPC> to Continue
_
DEC DC21140 (rev 0x2000022) at 0x80810000, irq 9, hwaddr 08:00:3e:c4:d6:9d
AMCC Motorola SEP/STP at 0x80840000, irq 14
SRI site reference/watchdog at 0x80000200, board rev. 2
Memory: 16535k/32768k available (76k kernel, 0k reserved)

Access Controller Gateway
Firmware Rev R02.03.02 (PowerPC)
Copyright (c) 1993-1996
Motorola, Inc.

Unauthorized Access Prohibited

Current status:

Active/Standby Status: UNKNOWN
MAC Address: 08:00:3e:c4:d6:9d

To enter configuration mode, hit any key within 10 seconds:
Waiting for ACTIVE/STANDBY status determination...
Booting from T1 interface (hit any key to abort).

ERROR - T1 initialization failed: Stabilization error

ERROR - T1 initialization failed: Stabilization error

ERROR - T1 initialization failed: Stabilization error
}}}

=== Menu === {{{
Enter "help" for a list of commands
ACG> help

Available commands:
dir - Show file directory
exit - Exit configuration mode
go - Execute application code
help - Print this info
inport - Dump input from a serial port
load - Load file into memory via ethernet
loadall - Load all files into memory via ethernet
nvr - Dump NVRAM
outport - Send output to a serial port
passwd - Change operator password
reset - Reboot this processor
sload - Load S-records from serial port
status - Print configuration parameters
ver - Print firmware version
ACG>
}}}

Images === Site Controller top view (lid removed) ===
Image(tetra_site_controller_open.jpg, 66%)

=== PCI Card with lots of Lucent chips ===
Image(tetra_site_controller_lucent_pcb_top.jpg, 50%)
Image(tetra_site_controller_lucent_pcb_bottom.jpg, 50%)

=== PCI Ethernet card (10-Base-2) ===
Image(tetra_site_controller_ethernet_pcb_top.jpg, 50%)

=== Clock card ===
Image(tetra_site_controller_clock_pcb_top.jpg, 50%)
Image(tetra_site_controller_clock_pcb_bottom.jpg, 50%)