Architecture » History » Version 4
Anonymous, 02/19/2016 10:52 PM
1 | 1 | = UmTRX architecture = |
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3 | 4 | The LMS6002D FPRF ICs provide analogue filtering, VGAs, VCOs and mixers etc. in addition to performing digital conversion. |
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5 | 4 | DC offset and IQ balance correction is implemented in the front-end in the FPGA. |
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7 | 4 | Host connection is via gigabit Ethernet and samples along with timestamps and system settings such as frequency, gain and bandwidth, are encapsulated in [http://www.vita.com/home/Specification/Specifications.html VITA Radio Transport] (VRT) packets. |
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9 | 4 | Higher TX and RX sample rates are used in the front-end than in communication with the host, and half-band and CIC filters implemented in the FPGA are used to perform up/down-conversion, with amplitude correction in place pre (RX) and post (TX) filtering. This allows the frequency to be shifted within the original sample rate and without having to re-tune the LMS6002D transceiver. |
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11 | After filtering, RX samples are immediately forwarded to the host by Ethernet packet router. |
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13 | TX packets received from the host are buffered by a SRAM FIFO to help ensure that there are always samples to transmit. |
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15 | RX samples are time-stamped and TX samples can be sent at a precise time, ensuring that TX and RX are perfectly aligned (this is critical for TDM systems). |
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17 | == High level == |
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19 | [[Image(UmTRX.png,75%)]] |
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21 | == FPGA == |
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23 | [[Image(FPGA_structure.png,50%)]] |