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/* xhfc24sucd.h
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* XHFC-2S4U / XHFC-4SU register definitions
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* (C) 2007, 2008 Copyright Cologne Chip AG
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* E-Mail: support@colognechip.com
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*
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* Dual-license
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* ------------
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* Cologne Chip AG, Eintrachtstr. 113, 50668 Koeln, Germany, provides this
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* header file (software) under a dual-license.
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* The licensee can choose from the following two licensing models:
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* * For GPL (free) distributions, see the 'License - GPL'
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* * For commercial distributions, see the 'License - Commercial'
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*
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*
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* License - GPL
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* -------------
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* This software is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2, or (at your option) any later version.
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*
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* This software is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details
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*
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* You should have received a copy of the GNU General Public License along with
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* this software; if not, write to the Free Software Foundation, Inc., 675 Mass
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* Ave, Cambridge, MA 02139, USA.
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*
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*
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* License - Commercial
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* --------------------
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* (C) 2007, 2008 Copyright Cologne Chip AG
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* All rights reserved.
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* Contact: support@CologneChip.com
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* * Redistributions of source code must mark all modifications explicitly
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* as such, if any are made.
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* * For redistributing and use of this software in binary form, none of the
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* provisions above applies.
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*
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* This software is provided by Cologne Chip AG "as is" and any express or
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* implied warranties, including, but not limited to, the implied warranties of
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* merchantability and fitness for a particular purpose are disclaimed. In no
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* event shall Cologne Chip AG be liable for any direct, indirect, incidental,
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* special, exemplary, or consequential damages (including, but not limited to,
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* procurement of substitute goods or services; loss of use, data, or profits;
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* or business interruption) however caused and on any theory of liability,
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* whether in contract, strict liability, or tort (including negligence or
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* otherwise) arising in any way out of the use of this software, even if
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* advised of the possibility of such damage.
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*
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* <END OF Dual-license>
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*
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* __________________________________________________________________________________
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*
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* File name: xhfc24sucd.h
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* File content: This file contains the XHFC-2S4U / XHFC-4SU register definitions.
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* Creation date: 18.06.2007 15:38
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* Creator: Genero 3.6
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* Data base: HFC XML 1.9 for XHFC-1SU, XHFC-2SU, XHFC-2S4U and XHFC-4SU
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* Address range: 0x00 - 0xFF
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*
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* The information presented can not be considered as assured characteristics.
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* Data can change without notice. Please check version numbers in case of doubt.
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*
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* For further information or questions please contact support@CologneChip.com
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* __________________________________________________________________________________
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*
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* WARNING: This file has been generated automatically and should not be
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* changed to maintain compatibility with later versions.
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* __________________________________________________________________________________
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*/
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#ifndef _XHFC24SUCD_H_
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#define _XHFC24SUCD_H_
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/*
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* Common chip information:
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*/
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#define CHIP_NAME_2S4U "XHFC-2S4U"
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#define CHIP_NAME_4SU "XHFC-4SU"
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#define CHIP_TITLE_2S4U "ISDN HDLC FIFO controller 2 S/T interfaces combined with 4 Up interfaces (Universal ISDN Ports)"
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#define CHIP_TITLE_4SU "ISDN HDLC FIFO controller with 4 S/T interfaces combined with 4 Up interfaces (Universal ISDN Ports)"
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#define CHIP_MANUFACTURER "Cologne Chip"
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#define CHIP_ID_2S4U 0x62
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#define CHIP_ID_4SU 0x63
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#define CHIP_REGISTER_COUNT 122
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#define CHIP_DATABASE "Version HFC-XMLHFC XML 1.9 for XHFC-1SU, XHFC-2SU, XHFC-2S4U and XHFC-4SU - GeneroGenero 3.6 "
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// This register file can also be used for XHFC-2SU and XHFC-1SU programming.
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// For this reason these chip names, IDs and titles are defined here as well:
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#define CHIP_NAME_2SU "XHFC-2SU"
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#define CHIP_TITLE_2SU "ISDN HDLC FIFO controller with 2 combined S/T and Up Interfaces"
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#define CHIP_ID_2SU 0x61
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#define CHIP_NAME_1SU "XHFC-1SU"
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#define CHIP_TITLE_1SU "ISDN HDLC FIFO controller with a combined S/T and Up Interface"
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#define CHIP_ID_1SU 0x60
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/*
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* Begin of XHFC-2S4U / XHFC-4SU register definitions.
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*/
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#define R_CIRM 0x00 // register address, write only
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#define M_CLK_OFF 0x01 // mask bit 0
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#define SET_V_CLK_OFF(R,V) (R = (__u8)((R & (__u8)(M_CLK_OFF ^ 0xFF)) | (__u8)(V & 0x01)))
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#define GET_V_CLK_OFF(R) (__u8)(R & M_CLK_OFF)
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#define M_WAIT_PROC 0x02 // mask bit 1
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#define SET_V_WAIT_PROC(R,V) (R = (__u8)((R & (__u8)(M_WAIT_PROC ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
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#define GET_V_WAIT_PROC(R) (__u8)((R & M_WAIT_PROC) >> 1)
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#define M_WAIT_REG 0x04 // mask bit 2
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#define SET_V_WAIT_REG(R,V) (R = (__u8)((R & (__u8)(M_WAIT_REG ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
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#define GET_V_WAIT_REG(R) (__u8)((R & M_WAIT_REG) >> 2)
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#define M_SRES 0x08 // mask bit 3
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#define SET_V_SRES(R,V) (R = (__u8)((R & (__u8)(M_SRES ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
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#define GET_V_SRES(R) (__u8)((R & M_SRES) >> 3)
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#define M_HFC_RES 0x10 // mask bit 4
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#define SET_V_HFC_RES(R,V) (R = (__u8)((R & (__u8)(M_HFC_RES ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
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#define GET_V_HFC_RES(R) (__u8)((R & M_HFC_RES) >> 4)
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#define M_PCM_RES 0x20 // mask bit 5
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#define SET_V_PCM_RES(R,V) (R = (__u8)((R & (__u8)(M_PCM_RES ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
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#define GET_V_PCM_RES(R) (__u8)((R & M_PCM_RES) >> 5)
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#define M_SU_RES 0x40 // mask bit 6
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#define SET_V_SU_RES(R,V) (R = (__u8)((R & (__u8)(M_SU_RES ^ 0xFF)) | (__u8)((V & 0x01) << 6)))
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#define GET_V_SU_RES(R) (__u8)((R & M_SU_RES) >> 6)
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#define R_CTRL 0x01 // register address, write only
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#define M_FIFO_LPRIO 0x02 // mask bit 1
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#define SET_V_FIFO_LPRIO(R,V) (R = (__u8)((R & (__u8)(M_FIFO_LPRIO ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
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#define GET_V_FIFO_LPRIO(R) (__u8)((R & M_FIFO_LPRIO) >> 1)
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#define M_NT_SYNC 0x08 // mask bit 3
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#define SET_V_NT_SYNC(R,V) (R = (__u8)((R & (__u8)(M_NT_SYNC ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
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#define GET_V_NT_SYNC(R) (__u8)((R & M_NT_SYNC) >> 3)
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#define M_OSC_OFF 0x20 // mask bit 5
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#define SET_V_OSC_OFF(R,V) (R = (__u8)((R & (__u8)(M_OSC_OFF ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
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#define GET_V_OSC_OFF(R) (__u8)((R & M_OSC_OFF) >> 5)
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#define M_SU_CLK 0xC0 // mask bits 6..7
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#define SET_V_SU_CLK(R,V) (R = (__u8)((R & (__u8)(M_SU_CLK ^ 0xFF)) | (__u8)((V & 0x03) << 6)))
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#define GET_V_SU_CLK(R) (__u8)((R & M_SU_CLK) >> 6)
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#define R_CLK_CFG 0x02 // register address, write only
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#define M_CLK_PLL 0x01 // mask bit 0
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#define SET_V_CLK_PLL(R,V) (R = (__u8)((R & (__u8)(M_CLK_PLL ^ 0xFF)) | (__u8)(V & 0x01)))
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#define GET_V_CLK_PLL(R) (__u8)(R & M_CLK_PLL)
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#define M_CLKO_HI 0x02 // mask bit 1
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#define SET_V_CLKO_HI(R,V) (R = (__u8)((R & (__u8)(M_CLKO_HI ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
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#define GET_V_CLKO_HI(R) (__u8)((R & M_CLKO_HI) >> 1)
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#define M_CLKO_PLL 0x04 // mask bit 2
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#define SET_V_CLKO_PLL(R,V) (R = (__u8)((R & (__u8)(M_CLKO_PLL ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
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#define GET_V_CLKO_PLL(R) (__u8)((R & M_CLKO_PLL) >> 2)
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#define M_PCM_CLK 0x20 // mask bit 5
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#define SET_V_PCM_CLK(R,V) (R = (__u8)((R & (__u8)(M_PCM_CLK ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
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#define GET_V_PCM_CLK(R) (__u8)((R & M_PCM_CLK) >> 5)
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#define M_CLKO_OFF 0x40 // mask bit 6
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#define SET_V_CLKO_OFF(R,V) (R = (__u8)((R & (__u8)(M_CLKO_OFF ^ 0xFF)) | (__u8)((V & 0x01) << 6)))
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#define GET_V_CLKO_OFF(R) (__u8)((R & M_CLKO_OFF) >> 6)
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#define M_CLK_F1 0x80 // mask bit 7
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#define SET_V_CLK_F1(R,V) (R = (__u8)((R & (__u8)(M_CLK_F1 ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
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#define GET_V_CLK_F1(R) (__u8)((R & M_CLK_F1) >> 7)
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#define A_Z1 0x04 // register address, read only
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#define M_Z1 0xFF // mask bits 0..7
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#define GET_V_Z1(R) (__u8)(R & M_Z1)
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#define A_Z2 0x06 // register address, read only
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#define M_Z2 0xFF // mask bits 0..7
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#define GET_V_Z2(R) (__u8)(R & M_Z2)
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#define R_RAM_ADDR 0x08 // register address, write only
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#define M_RAM_ADDR0 0xFF // mask bits 0..7
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#define SET_V_RAM_ADDR0(R,V) (R = (__u8)((R & (__u8)(M_RAM_ADDR0 ^ 0xFF)) | (__u8)V))
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#define GET_V_RAM_ADDR0(R) (__u8)(R & M_RAM_ADDR0)
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#define R_RAM_CTRL 0x09 // register address, write only
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#define M_RAM_ADDR1 0x0F // mask bits 0..3
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#define SET_V_RAM_ADDR1(R,V) (R = (__u8)((R & (__u8)(M_RAM_ADDR1 ^ 0xFF)) | (__u8)(V & 0x0F)))
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#define GET_V_RAM_ADDR1(R) (__u8)(R & M_RAM_ADDR1)
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#define M_ADDR_RES 0x40 // mask bit 6
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#define SET_V_ADDR_RES(R,V) (R = (__u8)((R & (__u8)(M_ADDR_RES ^ 0xFF)) | (__u8)((V & 0x01) << 6)))
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#define GET_V_ADDR_RES(R) (__u8)((R & M_ADDR_RES) >> 6)
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#define M_ADDR_INC 0x80 // mask bit 7
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#define SET_V_ADDR_INC(R,V) (R = (__u8)((R & (__u8)(M_ADDR_INC ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
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#define GET_V_ADDR_INC(R) (__u8)((R & M_ADDR_INC) >> 7)
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#define R_FIRST_FIFO 0x0B // register address, write only
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#define M_FIRST_FIFO_DIR 0x01 // mask bit 0
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#define SET_V_FIRST_FIFO_DIR(R,V) (R = (__u8)((R & (__u8)(M_FIRST_FIFO_DIR ^ 0xFF)) | (__u8)(V & 0x01)))
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#define GET_V_FIRST_FIFO_DIR(R) (__u8)(R & M_FIRST_FIFO_DIR)
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#define M_FIRST_FIFO_NUM 0x1E // mask bits 1..4
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#define SET_V_FIRST_FIFO_NUM(R,V) (R = (__u8)((R & (__u8)(M_FIRST_FIFO_NUM ^ 0xFF)) | (__u8)((V & 0x0F) << 1)))
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#define GET_V_FIRST_FIFO_NUM(R) (__u8)((R & M_FIRST_FIFO_NUM) >> 1)
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#define R_FIFO_THRES 0x0C // register address, write only
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#define M_THRES_TX 0x0F // mask bits 0..3
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#define SET_V_THRES_TX(R,V) (R = (__u8)((R & (__u8)(M_THRES_TX ^ 0xFF)) | (__u8)(V & 0x0F)))
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#define GET_V_THRES_TX(R) (__u8)(R & M_THRES_TX)
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#define M_THRES_RX 0xF0 // mask bits 4..7
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#define SET_V_THRES_RX(R,V) (R = (__u8)((R & (__u8)(M_THRES_RX ^ 0xFF)) | (__u8)((V & 0x0F) << 4)))
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#define GET_V_THRES_RX(R) (__u8)((R & M_THRES_RX) >> 4)
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#define A_F1 0x0C // register address, read only
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#define M_F1 0xFF // mask bits 0..7
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#define GET_V_F1(R) (__u8)(R & M_F1)
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#define R_FIFO_MD 0x0D // register address, write only
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#define M_FIFO_MD 0x03 // mask bits 0..1
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#define SET_V_FIFO_MD(R,V) (R = (__u8)((R & (__u8)(M_FIFO_MD ^ 0xFF)) | (__u8)(V & 0x03)))
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#define GET_V_FIFO_MD(R) (__u8)(R & M_FIFO_MD)
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#define M_DF_MD 0x0C // mask bits 2..3
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#define SET_V_DF_MD(R,V) (R = (__u8)((R & (__u8)(M_DF_MD ^ 0xFF)) | (__u8)((V & 0x03) << 2)))
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#define GET_V_DF_MD(R) (__u8)((R & M_DF_MD) >> 2)
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#define M_UNIDIR_MD 0x10 // mask bit 4
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#define SET_V_UNIDIR_MD(R,V) (R = (__u8)((R & (__u8)(M_UNIDIR_MD ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
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#define GET_V_UNIDIR_MD(R) (__u8)((R & M_UNIDIR_MD) >> 4)
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#define M_UNIDIR_RX 0x20 // mask bit 5
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#define SET_V_UNIDIR_RX(R,V) (R = (__u8)((R & (__u8)(M_UNIDIR_RX ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
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#define GET_V_UNIDIR_RX(R) (__u8)((R & M_UNIDIR_RX) >> 5)
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#define A_F2 0x0D // register address, read only
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#define M_F2 0xFF // mask bits 0..7
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#define GET_V_F2(R) (__u8)(R & M_F2)
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#define A_INC_RES_FIFO 0x0E // register address, write only
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#define M_INC_F 0x01 // mask bit 0
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#define SET_V_INC_F(R,V) (R = (__u8)((R & (__u8)(M_INC_F ^ 0xFF)) | (__u8)(V & 0x01)))
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#define GET_V_INC_F(R) (__u8)(R & M_INC_F)
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#define M_RES_FIFO 0x02 // mask bit 1
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#define SET_V_RES_FIFO(R,V) (R = (__u8)((R & (__u8)(M_RES_FIFO ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
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#define GET_V_RES_FIFO(R) (__u8)((R & M_RES_FIFO) >> 1)
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#define M_RES_LOST 0x04 // mask bit 2
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#define SET_V_RES_LOST(R,V) (R = (__u8)((R & (__u8)(M_RES_LOST ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
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#define GET_V_RES_LOST(R) (__u8)((R & M_RES_LOST) >> 2)
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#define M_RES_FIFO_ERR 0x08 // mask bit 3
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#define SET_V_RES_FIFO_ERR(R,V) (R = (__u8)((R & (__u8)(M_RES_FIFO_ERR ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
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#define GET_V_RES_FIFO_ERR(R) (__u8)((R & M_RES_FIFO_ERR) >> 3)
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#define A_FIFO_STA 0x0E // register address, read only
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#define M_FIFO_ERR 0x01 // mask bit 0
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#define GET_V_FIFO_ERR(R) (__u8)(R & M_FIFO_ERR)
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#define M_ABO_DONE 0x10 // mask bit 4
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286 |
#define GET_V_ABO_DONE(R) (__u8)((R & M_ABO_DONE) >> 4)
|
|
287 |
|
|
288 |
|
|
289 |
#define R_FSM_IDX 0x0F // register address, write only
|
|
290 |
#define M_IDX 0x1F // mask bits 0..4
|
|
291 |
#define SET_V_IDX(R,V) (R = (__u8)((R & (__u8)(M_IDX ^ 0xFF)) | (__u8)(V & 0x1F)))
|
|
292 |
#define GET_V_IDX(R) (__u8)(R & M_IDX)
|
|
293 |
|
|
294 |
|
|
295 |
#define R_FIFO 0x0F // register address, write only
|
|
296 |
#define M_FIFO_DIR 0x01 // mask bit 0
|
|
297 |
#define SET_V_FIFO_DIR(R,V) (R = (__u8)((R & (__u8)(M_FIFO_DIR ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
298 |
#define GET_V_FIFO_DIR(R) (__u8)(R & M_FIFO_DIR)
|
|
299 |
|
|
300 |
#define M_FIFO_NUM 0x1E // mask bits 1..4
|
|
301 |
#define SET_V_FIFO_NUM(R,V) (R = (__u8)((R & (__u8)(M_FIFO_NUM ^ 0xFF)) | (__u8)((V & 0x0F) << 1)))
|
|
302 |
#define GET_V_FIFO_NUM(R) (__u8)((R & M_FIFO_NUM) >> 1)
|
|
303 |
|
|
304 |
#define M_REV 0x80 // mask bit 7
|
|
305 |
#define SET_V_REV(R,V) (R = (__u8)((R & (__u8)(M_REV ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
306 |
#define GET_V_REV(R) (__u8)((R & M_REV) >> 7)
|
|
307 |
|
|
308 |
|
|
309 |
#define R_SLOT 0x10 // register address, write only
|
|
310 |
#define M_SL_DIR 0x01 // mask bit 0
|
|
311 |
#define SET_V_SL_DIR(R,V) (R = (__u8)((R & (__u8)(M_SL_DIR ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
312 |
#define GET_V_SL_DIR(R) (__u8)(R & M_SL_DIR)
|
|
313 |
|
|
314 |
#define M_SL_NUM 0xFE // mask bits 1..7
|
|
315 |
#define SET_V_SL_NUM(R,V) (R = (__u8)((R & (__u8)(M_SL_NUM ^ 0xFF)) | (__u8)((V & 0x7F) << 1)))
|
|
316 |
#define GET_V_SL_NUM(R) (__u8)((R & M_SL_NUM) >> 1)
|
|
317 |
|
|
318 |
|
|
319 |
#define R_IRQ_OVIEW 0x10 // register address, read only
|
|
320 |
#define M_FIFO_BL0_IRQ 0x01 // mask bit 0
|
|
321 |
#define GET_V_FIFO_BL0_IRQ(R) (__u8)(R & M_FIFO_BL0_IRQ)
|
|
322 |
|
|
323 |
#define M_FIFO_BL1_IRQ 0x02 // mask bit 1
|
|
324 |
#define GET_V_FIFO_BL1_IRQ(R) (__u8)((R & M_FIFO_BL1_IRQ) >> 1)
|
|
325 |
|
|
326 |
#define M_FIFO_BL2_IRQ 0x04 // mask bit 2
|
|
327 |
#define GET_V_FIFO_BL2_IRQ(R) (__u8)((R & M_FIFO_BL2_IRQ) >> 2)
|
|
328 |
|
|
329 |
#define M_FIFO_BL3_IRQ 0x08 // mask bit 3
|
|
330 |
#define GET_V_FIFO_BL3_IRQ(R) (__u8)((R & M_FIFO_BL3_IRQ) >> 3)
|
|
331 |
|
|
332 |
#define M_MISC_IRQ 0x10 // mask bit 4
|
|
333 |
#define GET_V_MISC_IRQ(R) (__u8)((R & M_MISC_IRQ) >> 4)
|
|
334 |
|
|
335 |
#define M_STUP_IRQ 0x20 // mask bit 5
|
|
336 |
#define GET_V_STUP_IRQ(R) (__u8)((R & M_STUP_IRQ) >> 5)
|
|
337 |
|
|
338 |
|
|
339 |
#define R_MISC_IRQMSK 0x11 // register address, write only
|
|
340 |
#define M_SLIP_IRQMSK 0x01 // mask bit 0
|
|
341 |
#define SET_V_SLIP_IRQMSK(R,V) (R = (__u8)((R & (__u8)(M_SLIP_IRQMSK ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
342 |
#define GET_V_SLIP_IRQMSK(R) (__u8)(R & M_SLIP_IRQMSK)
|
|
343 |
|
|
344 |
#define M_TI_IRQMSK 0x02 // mask bit 1
|
|
345 |
#define SET_V_TI_IRQMSK(R,V) (R = (__u8)((R & (__u8)(M_TI_IRQMSK ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
|
|
346 |
#define GET_V_TI_IRQMSK(R) (__u8)((R & M_TI_IRQMSK) >> 1)
|
|
347 |
|
|
348 |
#define M_PROC_IRQMSK 0x04 // mask bit 2
|
|
349 |
#define SET_V_PROC_IRQMSK(R,V) (R = (__u8)((R & (__u8)(M_PROC_IRQMSK ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
|
|
350 |
#define GET_V_PROC_IRQMSK(R) (__u8)((R & M_PROC_IRQMSK) >> 2)
|
|
351 |
|
|
352 |
#define M_CI_IRQMSK 0x10 // mask bit 4
|
|
353 |
#define SET_V_CI_IRQMSK(R,V) (R = (__u8)((R & (__u8)(M_CI_IRQMSK ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
|
|
354 |
#define GET_V_CI_IRQMSK(R) (__u8)((R & M_CI_IRQMSK) >> 4)
|
|
355 |
|
|
356 |
#define M_WAK_IRQMSK 0x20 // mask bit 5
|
|
357 |
#define SET_V_WAK_IRQMSK(R,V) (R = (__u8)((R & (__u8)(M_WAK_IRQMSK ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
|
|
358 |
#define GET_V_WAK_IRQMSK(R) (__u8)((R & M_WAK_IRQMSK) >> 5)
|
|
359 |
|
|
360 |
#define M_MON_TX_IRQMSK 0x40 // mask bit 6
|
|
361 |
#define SET_V_MON_TX_IRQMSK(R,V) (R = (__u8)((R & (__u8)(M_MON_TX_IRQMSK ^ 0xFF)) | (__u8)((V & 0x01) << 6)))
|
|
362 |
#define GET_V_MON_TX_IRQMSK(R) (__u8)((R & M_MON_TX_IRQMSK) >> 6)
|
|
363 |
|
|
364 |
#define M_MON_RX_IRQMSK 0x80 // mask bit 7
|
|
365 |
#define SET_V_MON_RX_IRQMSK(R,V) (R = (__u8)((R & (__u8)(M_MON_RX_IRQMSK ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
366 |
#define GET_V_MON_RX_IRQMSK(R) (__u8)((R & M_MON_RX_IRQMSK) >> 7)
|
|
367 |
|
|
368 |
|
|
369 |
#define R_MISC_IRQ 0x11 // register address, read only
|
|
370 |
#define M_SLIP_IRQ 0x01 // mask bit 0
|
|
371 |
#define GET_V_SLIP_IRQ(R) (__u8)(R & M_SLIP_IRQ)
|
|
372 |
|
|
373 |
#define M_TI_IRQ 0x02 // mask bit 1
|
|
374 |
#define GET_V_TI_IRQ(R) (__u8)((R & M_TI_IRQ) >> 1)
|
|
375 |
|
|
376 |
#define M_PROC_IRQ 0x04 // mask bit 2
|
|
377 |
#define GET_V_PROC_IRQ(R) (__u8)((R & M_PROC_IRQ) >> 2)
|
|
378 |
|
|
379 |
#define M_CI_IRQ 0x10 // mask bit 4
|
|
380 |
#define GET_V_CI_IRQ(R) (__u8)((R & M_CI_IRQ) >> 4)
|
|
381 |
|
|
382 |
#define M_WAK_IRQ 0x20 // mask bit 5
|
|
383 |
#define GET_V_WAK_IRQ(R) (__u8)((R & M_WAK_IRQ) >> 5)
|
|
384 |
|
|
385 |
#define M_MON_TX_IRQ 0x40 // mask bit 6
|
|
386 |
#define GET_V_MON_TX_IRQ(R) (__u8)((R & M_MON_TX_IRQ) >> 6)
|
|
387 |
|
|
388 |
#define M_MON_RX_IRQ 0x80 // mask bit 7
|
|
389 |
#define GET_V_MON_RX_IRQ(R) (__u8)((R & M_MON_RX_IRQ) >> 7)
|
|
390 |
|
|
391 |
|
|
392 |
#define R_SU_IRQ 0x12 // register address, read only
|
|
393 |
#define M_SU0_IRQ 0x01 // mask bit 0
|
|
394 |
#define GET_V_SU0_IRQ(R) (__u8)(R & M_SU0_IRQ)
|
|
395 |
|
|
396 |
#define M_SU1_IRQ 0x02 // mask bit 1
|
|
397 |
#define GET_V_SU1_IRQ(R) (__u8)((R & M_SU1_IRQ) >> 1)
|
|
398 |
|
|
399 |
#define M_SU2_IRQ 0x04 // mask bit 2
|
|
400 |
#define GET_V_SU2_IRQ(R) (__u8)((R & M_SU2_IRQ) >> 2)
|
|
401 |
|
|
402 |
#define M_SU3_IRQ 0x08 // mask bit 3
|
|
403 |
#define GET_V_SU3_IRQ(R) (__u8)((R & M_SU3_IRQ) >> 3)
|
|
404 |
|
|
405 |
|
|
406 |
#define R_SU_IRQMSK 0x12 // register address, write only
|
|
407 |
#define M_SU0_IRQMSK 0x01 // mask bit 0
|
|
408 |
#define SET_V_SU0_IRQMSK(R,V) (R = (__u8)((R & (__u8)(M_SU0_IRQMSK ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
409 |
#define GET_V_SU0_IRQMSK(R) (__u8)(R & M_SU0_IRQMSK)
|
|
410 |
|
|
411 |
#define M_SU1_IRQMSK 0x02 // mask bit 1
|
|
412 |
#define SET_V_SU1_IRQMSK(R,V) (R = (__u8)((R & (__u8)(M_SU1_IRQMSK ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
|
|
413 |
#define GET_V_SU1_IRQMSK(R) (__u8)((R & M_SU1_IRQMSK) >> 1)
|
|
414 |
|
|
415 |
#define M_SU2_IRQMSK 0x04 // mask bit 2
|
|
416 |
#define SET_V_SU2_IRQMSK(R,V) (R = (__u8)((R & (__u8)(M_SU2_IRQMSK ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
|
|
417 |
#define GET_V_SU2_IRQMSK(R) (__u8)((R & M_SU2_IRQMSK) >> 2)
|
|
418 |
|
|
419 |
#define M_SU3_IRQMSK 0x08 // mask bit 3
|
|
420 |
#define SET_V_SU3_IRQMSK(R,V) (R = (__u8)((R & (__u8)(M_SU3_IRQMSK ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
421 |
#define GET_V_SU3_IRQMSK(R) (__u8)((R & M_SU3_IRQMSK) >> 3)
|
|
422 |
|
|
423 |
|
|
424 |
#define R_AF0_OVIEW 0x13 // register address, read only
|
|
425 |
#define M_SU0_AF0 0x01 // mask bit 0
|
|
426 |
#define GET_V_SU0_AF0(R) (__u8)(R & M_SU0_AF0)
|
|
427 |
|
|
428 |
#define M_SU1_AF0 0x02 // mask bit 1
|
|
429 |
#define GET_V_SU1_AF0(R) (__u8)((R & M_SU1_AF0) >> 1)
|
|
430 |
|
|
431 |
#define M_SU2_AF0 0x04 // mask bit 2
|
|
432 |
#define GET_V_SU2_AF0(R) (__u8)((R & M_SU2_AF0) >> 2)
|
|
433 |
|
|
434 |
#define M_SU3_AF0 0x08 // mask bit 3
|
|
435 |
#define GET_V_SU3_AF0(R) (__u8)((R & M_SU3_AF0) >> 3)
|
|
436 |
|
|
437 |
|
|
438 |
#define R_IRQ_CTRL 0x13 // register address, write only
|
|
439 |
#define M_FIFO_IRQ_EN 0x01 // mask bit 0
|
|
440 |
#define SET_V_FIFO_IRQ_EN(R,V) (R = (__u8)((R & (__u8)(M_FIFO_IRQ_EN ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
441 |
#define GET_V_FIFO_IRQ_EN(R) (__u8)(R & M_FIFO_IRQ_EN)
|
|
442 |
|
|
443 |
#define M_GLOB_IRQ_EN 0x08 // mask bit 3
|
|
444 |
#define SET_V_GLOB_IRQ_EN(R,V) (R = (__u8)((R & (__u8)(M_GLOB_IRQ_EN ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
445 |
#define GET_V_GLOB_IRQ_EN(R) (__u8)((R & M_GLOB_IRQ_EN) >> 3)
|
|
446 |
|
|
447 |
#define M_IRQ_POL 0x10 // mask bit 4
|
|
448 |
#define SET_V_IRQ_POL(R,V) (R = (__u8)((R & (__u8)(M_IRQ_POL ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
|
|
449 |
#define GET_V_IRQ_POL(R) (__u8)((R & M_IRQ_POL) >> 4)
|
|
450 |
|
|
451 |
|
|
452 |
#define A_USAGE 0x14 // register address, read only
|
|
453 |
#define M_USAGE 0xFF // mask bits 0..7
|
|
454 |
#define GET_V_USAGE(R) (__u8)(R & M_USAGE)
|
|
455 |
|
|
456 |
|
|
457 |
#define R_PCM_MD0 0x14 // register address, write only
|
|
458 |
#define M_PCM_MD 0x01 // mask bit 0
|
|
459 |
#define SET_V_PCM_MD(R,V) (R = (__u8)((R & (__u8)(M_PCM_MD ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
460 |
#define GET_V_PCM_MD(R) (__u8)(R & M_PCM_MD)
|
|
461 |
|
|
462 |
#define M_C4_POL 0x02 // mask bit 1
|
|
463 |
#define SET_V_C4_POL(R,V) (R = (__u8)((R & (__u8)(M_C4_POL ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
|
|
464 |
#define GET_V_C4_POL(R) (__u8)((R & M_C4_POL) >> 1)
|
|
465 |
|
|
466 |
#define M_F0_NEG 0x04 // mask bit 2
|
|
467 |
#define SET_V_F0_NEG(R,V) (R = (__u8)((R & (__u8)(M_F0_NEG ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
|
|
468 |
#define GET_V_F0_NEG(R) (__u8)((R & M_F0_NEG) >> 2)
|
|
469 |
|
|
470 |
#define M_F0_LEN 0x08 // mask bit 3
|
|
471 |
#define SET_V_F0_LEN(R,V) (R = (__u8)((R & (__u8)(M_F0_LEN ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
472 |
#define GET_V_F0_LEN(R) (__u8)((R & M_F0_LEN) >> 3)
|
|
473 |
|
|
474 |
#define M_PCM_IDX 0xF0 // mask bits 4..7
|
|
475 |
#define SET_V_PCM_IDX(R,V) (R = (__u8)((R & (__u8)(M_PCM_IDX ^ 0xFF)) | (__u8)((V & 0x0F) << 4)))
|
|
476 |
#define GET_V_PCM_IDX(R) (__u8)((R & M_PCM_IDX) >> 4)
|
|
477 |
|
|
478 |
|
|
479 |
#define R_SL_SEL0 0x15 // register address, write only
|
|
480 |
#define M_SL_SEL0 0x7F // mask bits 0..6
|
|
481 |
#define SET_V_SL_SEL0(R,V) (R = (__u8)((R & (__u8)(M_SL_SEL0 ^ 0xFF)) | (__u8)(V & 0x7F)))
|
|
482 |
#define GET_V_SL_SEL0(R) (__u8)(R & M_SL_SEL0)
|
|
483 |
|
|
484 |
#define M_SH_SEL0 0x80 // mask bit 7
|
|
485 |
#define SET_V_SH_SEL0(R,V) (R = (__u8)((R & (__u8)(M_SH_SEL0 ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
486 |
#define GET_V_SH_SEL0(R) (__u8)((R & M_SH_SEL0) >> 7)
|
|
487 |
|
|
488 |
|
|
489 |
#define R_SL_SEL1 0x15 // register address, write only
|
|
490 |
#define M_SL_SEL1 0x7F // mask bits 0..6
|
|
491 |
#define SET_V_SL_SEL1(R,V) (R = (__u8)((R & (__u8)(M_SL_SEL1 ^ 0xFF)) | (__u8)(V & 0x7F)))
|
|
492 |
#define GET_V_SL_SEL1(R) (__u8)(R & M_SL_SEL1)
|
|
493 |
|
|
494 |
#define M_SH_SEL1 0x80 // mask bit 7
|
|
495 |
#define SET_V_SH_SEL1(R,V) (R = (__u8)((R & (__u8)(M_SH_SEL1 ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
496 |
#define GET_V_SH_SEL1(R) (__u8)((R & M_SH_SEL1) >> 7)
|
|
497 |
|
|
498 |
|
|
499 |
#define R_SL_SEL7 0x15 // register address, write only
|
|
500 |
#define M_SL_SEL7 0x7F // mask bits 0..6
|
|
501 |
#define SET_V_SL_SEL7(R,V) (R = (__u8)((R & (__u8)(M_SL_SEL7 ^ 0xFF)) | (__u8)(V & 0x7F)))
|
|
502 |
#define GET_V_SL_SEL7(R) (__u8)(R & M_SL_SEL7)
|
|
503 |
|
|
504 |
|
|
505 |
#define R_MSS0 0x15 // register address, write only
|
|
506 |
#define M_MSS_MOD 0x01 // mask bit 0
|
|
507 |
#define SET_V_MSS_MOD(R,V) (R = (__u8)((R & (__u8)(M_MSS_MOD ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
508 |
#define GET_V_MSS_MOD(R) (__u8)(R & M_MSS_MOD)
|
|
509 |
|
|
510 |
#define M_MSS_MOD_REP 0x02 // mask bit 1
|
|
511 |
#define SET_V_MSS_MOD_REP(R,V) (R = (__u8)((R & (__u8)(M_MSS_MOD_REP ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
|
|
512 |
#define GET_V_MSS_MOD_REP(R) (__u8)((R & M_MSS_MOD_REP) >> 1)
|
|
513 |
|
|
514 |
#define M_MSS_SRC_EN 0x04 // mask bit 2
|
|
515 |
#define SET_V_MSS_SRC_EN(R,V) (R = (__u8)((R & (__u8)(M_MSS_SRC_EN ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
|
|
516 |
#define GET_V_MSS_SRC_EN(R) (__u8)((R & M_MSS_SRC_EN) >> 2)
|
|
517 |
|
|
518 |
#define M_MSS_SRC_GRD 0x08 // mask bit 3
|
|
519 |
#define SET_V_MSS_SRC_GRD(R,V) (R = (__u8)((R & (__u8)(M_MSS_SRC_GRD ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
520 |
#define GET_V_MSS_SRC_GRD(R) (__u8)((R & M_MSS_SRC_GRD) >> 3)
|
|
521 |
|
|
522 |
#define M_MSS_OUT_EN 0x10 // mask bit 4
|
|
523 |
#define SET_V_MSS_OUT_EN(R,V) (R = (__u8)((R & (__u8)(M_MSS_OUT_EN ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
|
|
524 |
#define GET_V_MSS_OUT_EN(R) (__u8)((R & M_MSS_OUT_EN) >> 4)
|
|
525 |
|
|
526 |
#define M_MSS_OUT_REP 0x20 // mask bit 5
|
|
527 |
#define SET_V_MSS_OUT_REP(R,V) (R = (__u8)((R & (__u8)(M_MSS_OUT_REP ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
|
|
528 |
#define GET_V_MSS_OUT_REP(R) (__u8)((R & M_MSS_OUT_REP) >> 5)
|
|
529 |
|
|
530 |
#define M_MSS_SRC 0xC0 // mask bits 6..7
|
|
531 |
#define SET_V_MSS_SRC(R,V) (R = (__u8)((R & (__u8)(M_MSS_SRC ^ 0xFF)) | (__u8)((V & 0x03) << 6)))
|
|
532 |
#define GET_V_MSS_SRC(R) (__u8)((R & M_MSS_SRC) >> 6)
|
|
533 |
|
|
534 |
|
|
535 |
#define R_PCM_MD1 0x15 // register address, write only
|
|
536 |
#define M_PCM_OD 0x02 // mask bit 1
|
|
537 |
#define SET_V_PCM_OD(R,V) (R = (__u8)((R & (__u8)(M_PCM_OD ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
|
|
538 |
#define GET_V_PCM_OD(R) (__u8)((R & M_PCM_OD) >> 1)
|
|
539 |
|
|
540 |
#define M_PLL_ADJ 0x0C // mask bits 2..3
|
|
541 |
#define SET_V_PLL_ADJ(R,V) (R = (__u8)((R & (__u8)(M_PLL_ADJ ^ 0xFF)) | (__u8)((V & 0x03) << 2)))
|
|
542 |
#define GET_V_PLL_ADJ(R) (__u8)((R & M_PLL_ADJ) >> 2)
|
|
543 |
|
|
544 |
#define M_PCM_DR 0x30 // mask bits 4..5
|
|
545 |
#define SET_V_PCM_DR(R,V) (R = (__u8)((R & (__u8)(M_PCM_DR ^ 0xFF)) | (__u8)((V & 0x03) << 4)))
|
|
546 |
#define GET_V_PCM_DR(R) (__u8)((R & M_PCM_DR) >> 4)
|
|
547 |
|
|
548 |
#define M_PCM_LOOP 0x40 // mask bit 6
|
|
549 |
#define SET_V_PCM_LOOP(R,V) (R = (__u8)((R & (__u8)(M_PCM_LOOP ^ 0xFF)) | (__u8)((V & 0x01) << 6)))
|
|
550 |
#define GET_V_PCM_LOOP(R) (__u8)((R & M_PCM_LOOP) >> 6)
|
|
551 |
|
|
552 |
#define M_PCM_SMPL 0x80 // mask bit 7
|
|
553 |
#define SET_V_PCM_SMPL(R,V) (R = (__u8)((R & (__u8)(M_PCM_SMPL ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
554 |
#define GET_V_PCM_SMPL(R) (__u8)((R & M_PCM_SMPL) >> 7)
|
|
555 |
|
|
556 |
|
|
557 |
#define R_PCM_MD2 0x15 // register address, write only
|
|
558 |
#define M_SYNC_OUT1 0x02 // mask bit 1
|
|
559 |
#define SET_V_SYNC_OUT1(R,V) (R = (__u8)((R & (__u8)(M_SYNC_OUT1 ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
|
|
560 |
#define GET_V_SYNC_OUT1(R) (__u8)((R & M_SYNC_OUT1) >> 1)
|
|
561 |
|
|
562 |
#define M_SYNC_SRC 0x04 // mask bit 2
|
|
563 |
#define SET_V_SYNC_SRC(R,V) (R = (__u8)((R & (__u8)(M_SYNC_SRC ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
|
|
564 |
#define GET_V_SYNC_SRC(R) (__u8)((R & M_SYNC_SRC) >> 2)
|
|
565 |
|
|
566 |
#define M_SYNC_OUT2 0x08 // mask bit 3
|
|
567 |
#define SET_V_SYNC_OUT2(R,V) (R = (__u8)((R & (__u8)(M_SYNC_OUT2 ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
568 |
#define GET_V_SYNC_OUT2(R) (__u8)((R & M_SYNC_OUT2) >> 3)
|
|
569 |
|
|
570 |
#define M_C2O_EN 0x10 // mask bit 4
|
|
571 |
#define SET_V_C2O_EN(R,V) (R = (__u8)((R & (__u8)(M_C2O_EN ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
|
|
572 |
#define GET_V_C2O_EN(R) (__u8)((R & M_C2O_EN) >> 4)
|
|
573 |
|
|
574 |
#define M_C2I_EN 0x20 // mask bit 5
|
|
575 |
#define SET_V_C2I_EN(R,V) (R = (__u8)((R & (__u8)(M_C2I_EN ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
|
|
576 |
#define GET_V_C2I_EN(R) (__u8)((R & M_C2I_EN) >> 5)
|
|
577 |
|
|
578 |
#define M_PLL_ICR 0x40 // mask bit 6
|
|
579 |
#define SET_V_PLL_ICR(R,V) (R = (__u8)((R & (__u8)(M_PLL_ICR ^ 0xFF)) | (__u8)((V & 0x01) << 6)))
|
|
580 |
#define GET_V_PLL_ICR(R) (__u8)((R & M_PLL_ICR) >> 6)
|
|
581 |
|
|
582 |
#define M_PLL_MAN 0x80 // mask bit 7
|
|
583 |
#define SET_V_PLL_MAN(R,V) (R = (__u8)((R & (__u8)(M_PLL_MAN ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
584 |
#define GET_V_PLL_MAN(R) (__u8)((R & M_PLL_MAN) >> 7)
|
|
585 |
|
|
586 |
|
|
587 |
#define R_MSS1 0x15 // register address, write only
|
|
588 |
#define M_MSS_OFFS 0x07 // mask bits 0..2
|
|
589 |
#define SET_V_MSS_OFFS(R,V) (R = (__u8)((R & (__u8)(M_MSS_OFFS ^ 0xFF)) | (__u8)(V & 0x07)))
|
|
590 |
#define GET_V_MSS_OFFS(R) (__u8)(R & M_MSS_OFFS)
|
|
591 |
|
|
592 |
#define M_MS_SSYNC1 0x08 // mask bit 3
|
|
593 |
#define SET_V_MS_SSYNC1(R,V) (R = (__u8)((R & (__u8)(M_MS_SSYNC1 ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
594 |
#define GET_V_MS_SSYNC1(R) (__u8)((R & M_MS_SSYNC1) >> 3)
|
|
595 |
|
|
596 |
#define M_MSS_DLY 0xF0 // mask bits 4..7
|
|
597 |
#define SET_V_MSS_DLY(R,V) (R = (__u8)((R & (__u8)(M_MSS_DLY ^ 0xFF)) | (__u8)((V & 0x0F) << 4)))
|
|
598 |
#define GET_V_MSS_DLY(R) (__u8)((R & M_MSS_DLY) >> 4)
|
|
599 |
|
|
600 |
|
|
601 |
#define R_SH0L 0x15 // register address, write only
|
|
602 |
#define M_SH0L 0xFF // mask bits 0..7
|
|
603 |
#define SET_V_SH0L(R,V) (R = (__u8)((R & (__u8)(M_SH0L ^ 0xFF)) | (__u8)V))
|
|
604 |
#define GET_V_SH0L(R) (__u8)(R & M_SH0L)
|
|
605 |
|
|
606 |
|
|
607 |
#define R_SH0H 0x15 // register address, write only
|
|
608 |
#define M_SH0H 0xFF // mask bits 0..7
|
|
609 |
#define SET_V_SH0H(R,V) (R = (__u8)((R & (__u8)(M_SH0H ^ 0xFF)) | (__u8)V))
|
|
610 |
#define GET_V_SH0H(R) (__u8)(R & M_SH0H)
|
|
611 |
|
|
612 |
|
|
613 |
#define R_SH1L 0x15 // register address, write only
|
|
614 |
#define M_SH1L 0xFF // mask bits 0..7
|
|
615 |
#define SET_V_SH1L(R,V) (R = (__u8)((R & (__u8)(M_SH1L ^ 0xFF)) | (__u8)V))
|
|
616 |
#define GET_V_SH1L(R) (__u8)(R & M_SH1L)
|
|
617 |
|
|
618 |
|
|
619 |
#define R_SH1H 0x15 // register address, write only
|
|
620 |
#define M_SH1H 0xFF // mask bits 0..7
|
|
621 |
#define SET_V_SH1H(R,V) (R = (__u8)((R & (__u8)(M_SH1H ^ 0xFF)) | (__u8)V))
|
|
622 |
#define GET_V_SH1H(R) (__u8)(R & M_SH1H)
|
|
623 |
|
|
624 |
|
|
625 |
#define R_RAM_USE 0x15 // register address, read only
|
|
626 |
#define M_SRAM_USE 0xFF // mask bits 0..7
|
|
627 |
#define GET_V_SRAM_USE(R) (__u8)(R & M_SRAM_USE)
|
|
628 |
|
|
629 |
|
|
630 |
#define R_SU_SEL 0x16 // register address, write only
|
|
631 |
#define M_SU_SEL 0x03 // mask bits 0..1
|
|
632 |
#define SET_V_SU_SEL(R,V) (R = (__u8)((R & (__u8)(M_SU_SEL ^ 0xFF)) | (__u8)(V & 0x03)))
|
|
633 |
#define GET_V_SU_SEL(R) (__u8)(R & M_SU_SEL)
|
|
634 |
|
|
635 |
#define M_MULT_SU 0x08 // mask bit 3
|
|
636 |
#define SET_V_MULT_SU(R,V) (R = (__u8)((R & (__u8)(M_MULT_SU ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
637 |
#define GET_V_MULT_SU(R) (__u8)((R & M_MULT_SU) >> 3)
|
|
638 |
|
|
639 |
|
|
640 |
#define R_CHIP_ID 0x16 // register address, read only
|
|
641 |
#define M_CHIP_ID 0xFF // mask bits 0..7
|
|
642 |
#define GET_V_CHIP_ID(R) (__u8)(R & M_CHIP_ID)
|
|
643 |
|
|
644 |
|
|
645 |
#define R_BERT_STA 0x17 // register address, read only
|
|
646 |
#define M_RD_SYNC_SRC 0x07 // mask bits 0..2
|
|
647 |
#define GET_V_RD_SYNC_SRC(R) (__u8)(R & M_RD_SYNC_SRC)
|
|
648 |
|
|
649 |
#define M_BERT_SYNC 0x10 // mask bit 4
|
|
650 |
#define GET_V_BERT_SYNC(R) (__u8)((R & M_BERT_SYNC) >> 4)
|
|
651 |
|
|
652 |
#define M_BERT_INV_DATA 0x20 // mask bit 5
|
|
653 |
#define GET_V_BERT_INV_DATA(R) (__u8)((R & M_BERT_INV_DATA) >> 5)
|
|
654 |
|
|
655 |
|
|
656 |
#define R_SU_SYNC 0x17 // register address, write only
|
|
657 |
#define M_SYNC_SEL 0x07 // mask bits 0..2
|
|
658 |
#define SET_V_SYNC_SEL(R,V) (R = (__u8)((R & (__u8)(M_SYNC_SEL ^ 0xFF)) | (__u8)(V & 0x07)))
|
|
659 |
#define GET_V_SYNC_SEL(R) (__u8)(R & M_SYNC_SEL)
|
|
660 |
|
|
661 |
#define M_MAN_SYNC 0x08 // mask bit 3
|
|
662 |
#define SET_V_MAN_SYNC(R,V) (R = (__u8)((R & (__u8)(M_MAN_SYNC ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
663 |
#define GET_V_MAN_SYNC(R) (__u8)((R & M_MAN_SYNC) >> 3)
|
|
664 |
|
|
665 |
#define M_AUTO_SYNCI 0x10 // mask bit 4
|
|
666 |
#define SET_V_AUTO_SYNCI(R,V) (R = (__u8)((R & (__u8)(M_AUTO_SYNCI ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
|
|
667 |
#define GET_V_AUTO_SYNCI(R) (__u8)((R & M_AUTO_SYNCI) >> 4)
|
|
668 |
|
|
669 |
#define M_D_MERGE_TX 0x20 // mask bit 5
|
|
670 |
#define SET_V_D_MERGE_TX(R,V) (R = (__u8)((R & (__u8)(M_D_MERGE_TX ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
|
|
671 |
#define GET_V_D_MERGE_TX(R) (__u8)((R & M_D_MERGE_TX) >> 5)
|
|
672 |
|
|
673 |
#define M_E_MERGE_RX 0x40 // mask bit 6
|
|
674 |
#define SET_V_E_MERGE_RX(R,V) (R = (__u8)((R & (__u8)(M_E_MERGE_RX ^ 0xFF)) | (__u8)((V & 0x01) << 6)))
|
|
675 |
#define GET_V_E_MERGE_RX(R) (__u8)((R & M_E_MERGE_RX) >> 6)
|
|
676 |
|
|
677 |
#define M_D_MERGE_RX 0x80 // mask bit 7
|
|
678 |
#define SET_V_D_MERGE_RX(R,V) (R = (__u8)((R & (__u8)(M_D_MERGE_RX ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
679 |
#define GET_V_D_MERGE_RX(R) (__u8)((R & M_D_MERGE_RX) >> 7)
|
|
680 |
|
|
681 |
|
|
682 |
#define R_F0_CNTL 0x18 // register address, read only
|
|
683 |
#define M_F0_CNTL 0xFF // mask bits 0..7
|
|
684 |
#define GET_V_F0_CNTL(R) (__u8)(R & M_F0_CNTL)
|
|
685 |
|
|
686 |
|
|
687 |
#define R_F0_CNTH 0x19 // register address, read only
|
|
688 |
#define M_F0_CNTH 0xFF // mask bits 0..7
|
|
689 |
#define GET_V_F0_CNTH(R) (__u8)(R & M_F0_CNTH)
|
|
690 |
|
|
691 |
|
|
692 |
#define R_BERT_ECL 0x1A // register address, read only
|
|
693 |
#define M_BERT_ECL 0xFF // mask bits 0..7
|
|
694 |
#define GET_V_BERT_ECL(R) (__u8)(R & M_BERT_ECL)
|
|
695 |
|
|
696 |
|
|
697 |
#define R_TI_WD 0x1A // register address, write only
|
|
698 |
#define M_EV_TS 0x0F // mask bits 0..3
|
|
699 |
#define SET_V_EV_TS(R,V) (R = (__u8)((R & (__u8)(M_EV_TS ^ 0xFF)) | (__u8)(V & 0x0F)))
|
|
700 |
#define GET_V_EV_TS(R) (__u8)(R & M_EV_TS)
|
|
701 |
|
|
702 |
#define M_WD_TS 0xF0 // mask bits 4..7
|
|
703 |
#define SET_V_WD_TS(R,V) (R = (__u8)((R & (__u8)(M_WD_TS ^ 0xFF)) | (__u8)((V & 0x0F) << 4)))
|
|
704 |
#define GET_V_WD_TS(R) (__u8)((R & M_WD_TS) >> 4)
|
|
705 |
|
|
706 |
|
|
707 |
#define R_BERT_ECH 0x1B // register address, read only
|
|
708 |
#define M_BERT_ECH 0xFF // mask bits 0..7
|
|
709 |
#define GET_V_BERT_ECH(R) (__u8)(R & M_BERT_ECH)
|
|
710 |
|
|
711 |
|
|
712 |
#define R_BERT_WD_MD 0x1B // register address, write only
|
|
713 |
#define M_PAT_SEQ 0x07 // mask bits 0..2
|
|
714 |
#define SET_V_PAT_SEQ(R,V) (R = (__u8)((R & (__u8)(M_PAT_SEQ ^ 0xFF)) | (__u8)(V & 0x07)))
|
|
715 |
#define GET_V_PAT_SEQ(R) (__u8)(R & M_PAT_SEQ)
|
|
716 |
|
|
717 |
#define M_BERT_ERR 0x08 // mask bit 3
|
|
718 |
#define SET_V_BERT_ERR(R,V) (R = (__u8)((R & (__u8)(M_BERT_ERR ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
719 |
#define GET_V_BERT_ERR(R) (__u8)((R & M_BERT_ERR) >> 3)
|
|
720 |
|
|
721 |
#define M_AUTO_WD_RES 0x20 // mask bit 5
|
|
722 |
#define SET_V_AUTO_WD_RES(R,V) (R = (__u8)((R & (__u8)(M_AUTO_WD_RES ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
|
|
723 |
#define GET_V_AUTO_WD_RES(R) (__u8)((R & M_AUTO_WD_RES) >> 5)
|
|
724 |
|
|
725 |
#define M_WD_RES 0x80 // mask bit 7
|
|
726 |
#define SET_V_WD_RES(R,V) (R = (__u8)((R & (__u8)(M_WD_RES ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
727 |
#define GET_V_WD_RES(R) (__u8)((R & M_WD_RES) >> 7)
|
|
728 |
|
|
729 |
|
|
730 |
#define R_STATUS 0x1C // register address, read only
|
|
731 |
#define M_BUSY 0x01 // mask bit 0
|
|
732 |
#define GET_V_BUSY(R) (__u8)(R & M_BUSY)
|
|
733 |
|
|
734 |
#define M_PROC 0x02 // mask bit 1
|
|
735 |
#define GET_V_PROC(R) (__u8)((R & M_PROC) >> 1)
|
|
736 |
|
|
737 |
#define M_LOST_STA 0x08 // mask bit 3
|
|
738 |
#define GET_V_LOST_STA(R) (__u8)((R & M_LOST_STA) >> 3)
|
|
739 |
|
|
740 |
#define M_PCM_INIT 0x10 // mask bit 4
|
|
741 |
#define GET_V_PCM_INIT(R) (__u8)((R & M_PCM_INIT) >> 4)
|
|
742 |
|
|
743 |
#define M_WAK_STA 0x20 // mask bit 5
|
|
744 |
#define GET_V_WAK_STA(R) (__u8)((R & M_WAK_STA) >> 5)
|
|
745 |
|
|
746 |
#define M_MISC_IRQSTA 0x40 // mask bit 6
|
|
747 |
#define GET_V_MISC_IRQSTA(R) (__u8)((R & M_MISC_IRQSTA) >> 6)
|
|
748 |
|
|
749 |
#define M_FIFO_IRQSTA 0x80 // mask bit 7
|
|
750 |
#define GET_V_FIFO_IRQSTA(R) (__u8)((R & M_FIFO_IRQSTA) >> 7)
|
|
751 |
|
|
752 |
|
|
753 |
#define R_SL_MAX 0x1D // register address, read only
|
|
754 |
#define M_SL_MAX 0xFF // mask bits 0..7
|
|
755 |
#define GET_V_SL_MAX(R) (__u8)(R & M_SL_MAX)
|
|
756 |
|
|
757 |
|
|
758 |
#define R_PWM_CFG 0x1E // register address, write only
|
|
759 |
#define M_PWM0_16KHZ 0x10 // mask bit 4
|
|
760 |
#define SET_V_PWM0_16KHZ(R,V) (R = (__u8)((R & (__u8)(M_PWM0_16KHZ ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
|
|
761 |
#define GET_V_PWM0_16KHZ(R) (__u8)((R & M_PWM0_16KHZ) >> 4)
|
|
762 |
|
|
763 |
#define M_PWM1_16KHZ 0x20 // mask bit 5
|
|
764 |
#define SET_V_PWM1_16KHZ(R,V) (R = (__u8)((R & (__u8)(M_PWM1_16KHZ ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
|
|
765 |
#define GET_V_PWM1_16KHZ(R) (__u8)((R & M_PWM1_16KHZ) >> 5)
|
|
766 |
|
|
767 |
#define M_PWM_FRQ 0xC0 // mask bits 6..7
|
|
768 |
#define SET_V_PWM_FRQ(R,V) (R = (__u8)((R & (__u8)(M_PWM_FRQ ^ 0xFF)) | (__u8)((V & 0x03) << 6)))
|
|
769 |
#define GET_V_PWM_FRQ(R) (__u8)((R & M_PWM_FRQ) >> 6)
|
|
770 |
|
|
771 |
|
|
772 |
#define R_CHIP_RV 0x1F // register address, read only
|
|
773 |
#define M_CHIP_RV 0x0F // mask bits 0..3
|
|
774 |
#define GET_V_CHIP_RV(R) (__u8)(R & M_CHIP_RV)
|
|
775 |
|
|
776 |
|
|
777 |
#define R_FIFO_BL0_IRQ 0x20 // register address, read only
|
|
778 |
#define M_FIFO0_TX_IRQ 0x01 // mask bit 0
|
|
779 |
#define GET_V_FIFO0_TX_IRQ(R) (__u8)(R & M_FIFO0_TX_IRQ)
|
|
780 |
|
|
781 |
#define M_FIFO0_RX_IRQ 0x02 // mask bit 1
|
|
782 |
#define GET_V_FIFO0_RX_IRQ(R) (__u8)((R & M_FIFO0_RX_IRQ) >> 1)
|
|
783 |
|
|
784 |
#define M_FIFO1_TX_IRQ 0x04 // mask bit 2
|
|
785 |
#define GET_V_FIFO1_TX_IRQ(R) (__u8)((R & M_FIFO1_TX_IRQ) >> 2)
|
|
786 |
|
|
787 |
#define M_FIFO1_RX_IRQ 0x08 // mask bit 3
|
|
788 |
#define GET_V_FIFO1_RX_IRQ(R) (__u8)((R & M_FIFO1_RX_IRQ) >> 3)
|
|
789 |
|
|
790 |
#define M_FIFO2_TX_IRQ 0x10 // mask bit 4
|
|
791 |
#define GET_V_FIFO2_TX_IRQ(R) (__u8)((R & M_FIFO2_TX_IRQ) >> 4)
|
|
792 |
|
|
793 |
#define M_FIFO2_RX_IRQ 0x20 // mask bit 5
|
|
794 |
#define GET_V_FIFO2_RX_IRQ(R) (__u8)((R & M_FIFO2_RX_IRQ) >> 5)
|
|
795 |
|
|
796 |
#define M_FIFO3_TX_IRQ 0x40 // mask bit 6
|
|
797 |
#define GET_V_FIFO3_TX_IRQ(R) (__u8)((R & M_FIFO3_TX_IRQ) >> 6)
|
|
798 |
|
|
799 |
#define M_FIFO3_RX_IRQ 0x80 // mask bit 7
|
|
800 |
#define GET_V_FIFO3_RX_IRQ(R) (__u8)((R & M_FIFO3_RX_IRQ) >> 7)
|
|
801 |
|
|
802 |
|
|
803 |
#define R_FIFO_BL1_IRQ 0x21 // register address, read only
|
|
804 |
#define M_FIFO4_TX_IRQ 0x01 // mask bit 0
|
|
805 |
#define GET_V_FIFO4_TX_IRQ(R) (__u8)(R & M_FIFO4_TX_IRQ)
|
|
806 |
|
|
807 |
#define M_FIFO4_RX_IRQ 0x02 // mask bit 1
|
|
808 |
#define GET_V_FIFO4_RX_IRQ(R) (__u8)((R & M_FIFO4_RX_IRQ) >> 1)
|
|
809 |
|
|
810 |
#define M_FIFO5_TX_IRQ 0x04 // mask bit 2
|
|
811 |
#define GET_V_FIFO5_TX_IRQ(R) (__u8)((R & M_FIFO5_TX_IRQ) >> 2)
|
|
812 |
|
|
813 |
#define M_FIFO5_RX_IRQ 0x08 // mask bit 3
|
|
814 |
#define GET_V_FIFO5_RX_IRQ(R) (__u8)((R & M_FIFO5_RX_IRQ) >> 3)
|
|
815 |
|
|
816 |
#define M_FIFO6_TX_IRQ 0x10 // mask bit 4
|
|
817 |
#define GET_V_FIFO6_TX_IRQ(R) (__u8)((R & M_FIFO6_TX_IRQ) >> 4)
|
|
818 |
|
|
819 |
#define M_FIFO6_RX_IRQ 0x20 // mask bit 5
|
|
820 |
#define GET_V_FIFO6_RX_IRQ(R) (__u8)((R & M_FIFO6_RX_IRQ) >> 5)
|
|
821 |
|
|
822 |
#define M_FIFO7_TX_IRQ 0x40 // mask bit 6
|
|
823 |
#define GET_V_FIFO7_TX_IRQ(R) (__u8)((R & M_FIFO7_TX_IRQ) >> 6)
|
|
824 |
|
|
825 |
#define M_FIFO7_RX_IRQ 0x80 // mask bit 7
|
|
826 |
#define GET_V_FIFO7_RX_IRQ(R) (__u8)((R & M_FIFO7_RX_IRQ) >> 7)
|
|
827 |
|
|
828 |
|
|
829 |
#define R_FIFO_BL2_IRQ 0x22 // register address, read only
|
|
830 |
#define M_FIFO8_TX_IRQ 0x01 // mask bit 0
|
|
831 |
#define GET_V_FIFO8_TX_IRQ(R) (__u8)(R & M_FIFO8_TX_IRQ)
|
|
832 |
|
|
833 |
#define M_FIFO8_RX_IRQ 0x02 // mask bit 1
|
|
834 |
#define GET_V_FIFO8_RX_IRQ(R) (__u8)((R & M_FIFO8_RX_IRQ) >> 1)
|
|
835 |
|
|
836 |
#define M_FIFO9_TX_IRQ 0x04 // mask bit 2
|
|
837 |
#define GET_V_FIFO9_TX_IRQ(R) (__u8)((R & M_FIFO9_TX_IRQ) >> 2)
|
|
838 |
|
|
839 |
#define M_FIFO9_RX_IRQ 0x08 // mask bit 3
|
|
840 |
#define GET_V_FIFO9_RX_IRQ(R) (__u8)((R & M_FIFO9_RX_IRQ) >> 3)
|
|
841 |
|
|
842 |
#define M_FIFO10_TX_IRQ 0x10 // mask bit 4
|
|
843 |
#define GET_V_FIFO10_TX_IRQ(R) (__u8)((R & M_FIFO10_TX_IRQ) >> 4)
|
|
844 |
|
|
845 |
#define M_FIFO10_RX_IRQ 0x20 // mask bit 5
|
|
846 |
#define GET_V_FIFO10_RX_IRQ(R) (__u8)((R & M_FIFO10_RX_IRQ) >> 5)
|
|
847 |
|
|
848 |
#define M_FIFO11_TX_IRQ 0x40 // mask bit 6
|
|
849 |
#define GET_V_FIFO11_TX_IRQ(R) (__u8)((R & M_FIFO11_TX_IRQ) >> 6)
|
|
850 |
|
|
851 |
#define M_FIFO11_RX_IRQ 0x80 // mask bit 7
|
|
852 |
#define GET_V_FIFO11_RX_IRQ(R) (__u8)((R & M_FIFO11_RX_IRQ) >> 7)
|
|
853 |
|
|
854 |
|
|
855 |
#define R_FIFO_BL3_IRQ 0x23 // register address, read only
|
|
856 |
#define M_FIFO12_TX_IRQ 0x01 // mask bit 0
|
|
857 |
#define GET_V_FIFO12_TX_IRQ(R) (__u8)(R & M_FIFO12_TX_IRQ)
|
|
858 |
|
|
859 |
#define M_FIFO12_RX_IRQ 0x02 // mask bit 1
|
|
860 |
#define GET_V_FIFO12_RX_IRQ(R) (__u8)((R & M_FIFO12_RX_IRQ) >> 1)
|
|
861 |
|
|
862 |
#define M_FIFO13_TX_IRQ 0x04 // mask bit 2
|
|
863 |
#define GET_V_FIFO13_TX_IRQ(R) (__u8)((R & M_FIFO13_TX_IRQ) >> 2)
|
|
864 |
|
|
865 |
#define M_FIFO13_RX_IRQ 0x08 // mask bit 3
|
|
866 |
#define GET_V_FIFO13_RX_IRQ(R) (__u8)((R & M_FIFO13_RX_IRQ) >> 3)
|
|
867 |
|
|
868 |
#define M_FIFO14_TX_IRQ 0x10 // mask bit 4
|
|
869 |
#define GET_V_FIFO14_TX_IRQ(R) (__u8)((R & M_FIFO14_TX_IRQ) >> 4)
|
|
870 |
|
|
871 |
#define M_FIFO14_RX_IRQ 0x20 // mask bit 5
|
|
872 |
#define GET_V_FIFO14_RX_IRQ(R) (__u8)((R & M_FIFO14_RX_IRQ) >> 5)
|
|
873 |
|
|
874 |
#define M_FIFO15_TX_IRQ 0x40 // mask bit 6
|
|
875 |
#define GET_V_FIFO15_TX_IRQ(R) (__u8)((R & M_FIFO15_TX_IRQ) >> 6)
|
|
876 |
|
|
877 |
#define M_FIFO15_RX_IRQ 0x80 // mask bit 7
|
|
878 |
#define GET_V_FIFO15_RX_IRQ(R) (__u8)((R & M_FIFO15_RX_IRQ) >> 7)
|
|
879 |
|
|
880 |
|
|
881 |
#define R_FILL_BL0 0x24 // register address, read only
|
|
882 |
#define M_FILL_FIFO0_TX 0x01 // mask bit 0
|
|
883 |
#define GET_V_FILL_FIFO0_TX(R) (__u8)(R & M_FILL_FIFO0_TX)
|
|
884 |
|
|
885 |
#define M_FILL_FIFO0_RX 0x02 // mask bit 1
|
|
886 |
#define GET_V_FILL_FIFO0_RX(R) (__u8)((R & M_FILL_FIFO0_RX) >> 1)
|
|
887 |
|
|
888 |
#define M_FILL_FIFO1_TX 0x04 // mask bit 2
|
|
889 |
#define GET_V_FILL_FIFO1_TX(R) (__u8)((R & M_FILL_FIFO1_TX) >> 2)
|
|
890 |
|
|
891 |
#define M_FILL_FIFO1_RX 0x08 // mask bit 3
|
|
892 |
#define GET_V_FILL_FIFO1_RX(R) (__u8)((R & M_FILL_FIFO1_RX) >> 3)
|
|
893 |
|
|
894 |
#define M_FILL_FIFO2_TX 0x10 // mask bit 4
|
|
895 |
#define GET_V_FILL_FIFO2_TX(R) (__u8)((R & M_FILL_FIFO2_TX) >> 4)
|
|
896 |
|
|
897 |
#define M_FILL_FIFO2_RX 0x20 // mask bit 5
|
|
898 |
#define GET_V_FILL_FIFO2_RX(R) (__u8)((R & M_FILL_FIFO2_RX) >> 5)
|
|
899 |
|
|
900 |
#define M_FILL_FIFO3_TX 0x40 // mask bit 6
|
|
901 |
#define GET_V_FILL_FIFO3_TX(R) (__u8)((R & M_FILL_FIFO3_TX) >> 6)
|
|
902 |
|
|
903 |
#define M_FILL_FIFO3_RX 0x80 // mask bit 7
|
|
904 |
#define GET_V_FILL_FIFO3_RX(R) (__u8)((R & M_FILL_FIFO3_RX) >> 7)
|
|
905 |
|
|
906 |
|
|
907 |
#define R_FILL_BL1 0x25 // register address, read only
|
|
908 |
#define M_FILL_FIFO4_TX 0x01 // mask bit 0
|
|
909 |
#define GET_V_FILL_FIFO4_TX(R) (__u8)(R & M_FILL_FIFO4_TX)
|
|
910 |
|
|
911 |
#define M_FILL_FIFO4_RX 0x02 // mask bit 1
|
|
912 |
#define GET_V_FILL_FIFO4_RX(R) (__u8)((R & M_FILL_FIFO4_RX) >> 1)
|
|
913 |
|
|
914 |
#define M_FILL_FIFO5_TX 0x04 // mask bit 2
|
|
915 |
#define GET_V_FILL_FIFO5_TX(R) (__u8)((R & M_FILL_FIFO5_TX) >> 2)
|
|
916 |
|
|
917 |
#define M_FILL_FIFO5_RX 0x08 // mask bit 3
|
|
918 |
#define GET_V_FILL_FIFO5_RX(R) (__u8)((R & M_FILL_FIFO5_RX) >> 3)
|
|
919 |
|
|
920 |
#define M_FILL_FIFO6_TX 0x10 // mask bit 4
|
|
921 |
#define GET_V_FILL_FIFO6_TX(R) (__u8)((R & M_FILL_FIFO6_TX) >> 4)
|
|
922 |
|
|
923 |
#define M_FILL_FIFO6_RX 0x20 // mask bit 5
|
|
924 |
#define GET_V_FILL_FIFO6_RX(R) (__u8)((R & M_FILL_FIFO6_RX) >> 5)
|
|
925 |
|
|
926 |
#define M_FILL_FIFO7_TX 0x40 // mask bit 6
|
|
927 |
#define GET_V_FILL_FIFO7_TX(R) (__u8)((R & M_FILL_FIFO7_TX) >> 6)
|
|
928 |
|
|
929 |
#define M_FILL_FIFO7_RX 0x80 // mask bit 7
|
|
930 |
#define GET_V_FILL_FIFO7_RX(R) (__u8)((R & M_FILL_FIFO7_RX) >> 7)
|
|
931 |
|
|
932 |
|
|
933 |
#define R_FILL_BL2 0x26 // register address, read only
|
|
934 |
#define M_FILL_FIFO8_TX 0x01 // mask bit 0
|
|
935 |
#define GET_V_FILL_FIFO8_TX(R) (__u8)(R & M_FILL_FIFO8_TX)
|
|
936 |
|
|
937 |
#define M_FILL_FIFO8_RX 0x02 // mask bit 1
|
|
938 |
#define GET_V_FILL_FIFO8_RX(R) (__u8)((R & M_FILL_FIFO8_RX) >> 1)
|
|
939 |
|
|
940 |
#define M_FILL_FIFO9_TX 0x04 // mask bit 2
|
|
941 |
#define GET_V_FILL_FIFO9_TX(R) (__u8)((R & M_FILL_FIFO9_TX) >> 2)
|
|
942 |
|
|
943 |
#define M_FILL_FIFO9_RX 0x08 // mask bit 3
|
|
944 |
#define GET_V_FILL_FIFO9_RX(R) (__u8)((R & M_FILL_FIFO9_RX) >> 3)
|
|
945 |
|
|
946 |
#define M_FILL_FIFO10_TX 0x10 // mask bit 4
|
|
947 |
#define GET_V_FILL_FIFO10_TX(R) (__u8)((R & M_FILL_FIFO10_TX) >> 4)
|
|
948 |
|
|
949 |
#define M_FILL_FIFO10_RX 0x20 // mask bit 5
|
|
950 |
#define GET_V_FILL_FIFO10_RX(R) (__u8)((R & M_FILL_FIFO10_RX) >> 5)
|
|
951 |
|
|
952 |
#define M_FILL_FIFO11_TX 0x40 // mask bit 6
|
|
953 |
#define GET_V_FILL_FIFO11_TX(R) (__u8)((R & M_FILL_FIFO11_TX) >> 6)
|
|
954 |
|
|
955 |
#define M_FILL_FIFO11_RX 0x80 // mask bit 7
|
|
956 |
#define GET_V_FILL_FIFO11_RX(R) (__u8)((R & M_FILL_FIFO11_RX) >> 7)
|
|
957 |
|
|
958 |
|
|
959 |
#define R_FILL_BL3 0x27 // register address, read only
|
|
960 |
#define M_FILL_FIFO12_TX 0x01 // mask bit 0
|
|
961 |
#define GET_V_FILL_FIFO12_TX(R) (__u8)(R & M_FILL_FIFO12_TX)
|
|
962 |
|
|
963 |
#define M_FILL_FIFO12_RX 0x02 // mask bit 1
|
|
964 |
#define GET_V_FILL_FIFO12_RX(R) (__u8)((R & M_FILL_FIFO12_RX) >> 1)
|
|
965 |
|
|
966 |
#define M_FILL_FIFO13_TX 0x04 // mask bit 2
|
|
967 |
#define GET_V_FILL_FIFO13_TX(R) (__u8)((R & M_FILL_FIFO13_TX) >> 2)
|
|
968 |
|
|
969 |
#define M_FILL_FIFO13_RX 0x08 // mask bit 3
|
|
970 |
#define GET_V_FILL_FIFO13_RX(R) (__u8)((R & M_FILL_FIFO13_RX) >> 3)
|
|
971 |
|
|
972 |
#define M_FILL_FIFO14_TX 0x10 // mask bit 4
|
|
973 |
#define GET_V_FILL_FIFO14_TX(R) (__u8)((R & M_FILL_FIFO14_TX) >> 4)
|
|
974 |
|
|
975 |
#define M_FILL_FIFO14_RX 0x20 // mask bit 5
|
|
976 |
#define GET_V_FILL_FIFO14_RX(R) (__u8)((R & M_FILL_FIFO14_RX) >> 5)
|
|
977 |
|
|
978 |
#define M_FILL_FIFO15_TX 0x40 // mask bit 6
|
|
979 |
#define GET_V_FILL_FIFO15_TX(R) (__u8)((R & M_FILL_FIFO15_TX) >> 6)
|
|
980 |
|
|
981 |
#define M_FILL_FIFO15_RX 0x80 // mask bit 7
|
|
982 |
#define GET_V_FILL_FIFO15_RX(R) (__u8)((R & M_FILL_FIFO15_RX) >> 7)
|
|
983 |
|
|
984 |
|
|
985 |
#define R_CI_TX 0x28 // register address, write only
|
|
986 |
#define M_GCI_C 0x3F // mask bits 0..5
|
|
987 |
#define SET_V_GCI_C(R,V) (R = (__u8)((R & (__u8)(M_GCI_C ^ 0xFF)) | (__u8)(V & 0x3F)))
|
|
988 |
#define GET_V_GCI_C(R) (__u8)(R & M_GCI_C)
|
|
989 |
|
|
990 |
|
|
991 |
#define R_CI_RX 0x28 // register address, read only
|
|
992 |
#define M_GCI_I 0x3F // mask bits 0..5
|
|
993 |
#define GET_V_GCI_I(R) (__u8)(R & M_GCI_I)
|
|
994 |
|
|
995 |
|
|
996 |
#define R_GCI_CFG0 0x29 // register address, write only
|
|
997 |
#define M_MON_END 0x01 // mask bit 0
|
|
998 |
#define SET_V_MON_END(R,V) (R = (__u8)((R & (__u8)(M_MON_END ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
999 |
#define GET_V_MON_END(R) (__u8)(R & M_MON_END)
|
|
1000 |
|
|
1001 |
#define M_MON_SLOW 0x02 // mask bit 1
|
|
1002 |
#define SET_V_MON_SLOW(R,V) (R = (__u8)((R & (__u8)(M_MON_SLOW ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
|
|
1003 |
#define GET_V_MON_SLOW(R) (__u8)((R & M_MON_SLOW) >> 1)
|
|
1004 |
|
|
1005 |
#define M_MON_DLL 0x04 // mask bit 2
|
|
1006 |
#define SET_V_MON_DLL(R,V) (R = (__u8)((R & (__u8)(M_MON_DLL ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
|
|
1007 |
#define GET_V_MON_DLL(R) (__u8)((R & M_MON_DLL) >> 2)
|
|
1008 |
|
|
1009 |
#define M_MON_CI6 0x08 // mask bit 3
|
|
1010 |
#define SET_V_MON_CI6(R,V) (R = (__u8)((R & (__u8)(M_MON_CI6 ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
1011 |
#define GET_V_MON_CI6(R) (__u8)((R & M_MON_CI6) >> 3)
|
|
1012 |
|
|
1013 |
#define M_GCI_SWAP_TXHS 0x10 // mask bit 4
|
|
1014 |
#define SET_V_GCI_SWAP_TXHS(R,V) (R = (__u8)((R & (__u8)(M_GCI_SWAP_TXHS ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
|
|
1015 |
#define GET_V_GCI_SWAP_TXHS(R) (__u8)((R & M_GCI_SWAP_TXHS) >> 4)
|
|
1016 |
|
|
1017 |
#define M_GCI_SWAP_RXHS 0x20 // mask bit 5
|
|
1018 |
#define SET_V_GCI_SWAP_RXHS(R,V) (R = (__u8)((R & (__u8)(M_GCI_SWAP_RXHS ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
|
|
1019 |
#define GET_V_GCI_SWAP_RXHS(R) (__u8)((R & M_GCI_SWAP_RXHS) >> 5)
|
|
1020 |
|
|
1021 |
#define M_GCI_SWAP_STIO 0x40 // mask bit 6
|
|
1022 |
#define SET_V_GCI_SWAP_STIO(R,V) (R = (__u8)((R & (__u8)(M_GCI_SWAP_STIO ^ 0xFF)) | (__u8)((V & 0x01) << 6)))
|
|
1023 |
#define GET_V_GCI_SWAP_STIO(R) (__u8)((R & M_GCI_SWAP_STIO) >> 6)
|
|
1024 |
|
|
1025 |
#define M_GCI_EN 0x80 // mask bit 7
|
|
1026 |
#define SET_V_GCI_EN(R,V) (R = (__u8)((R & (__u8)(M_GCI_EN ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
1027 |
#define GET_V_GCI_EN(R) (__u8)((R & M_GCI_EN) >> 7)
|
|
1028 |
|
|
1029 |
|
|
1030 |
#define R_GCI_STA 0x29 // register address, read only
|
|
1031 |
#define M_MON_RXR 0x01 // mask bit 0
|
|
1032 |
#define GET_V_MON_RXR(R) (__u8)(R & M_MON_RXR)
|
|
1033 |
|
|
1034 |
#define M_MON_TXR 0x02 // mask bit 1
|
|
1035 |
#define GET_V_MON_TXR(R) (__u8)((R & M_MON_TXR) >> 1)
|
|
1036 |
|
|
1037 |
#define M_GCI_MX 0x04 // mask bit 2
|
|
1038 |
#define GET_V_GCI_MX(R) (__u8)((R & M_GCI_MX) >> 2)
|
|
1039 |
|
|
1040 |
#define M_GCI_MR 0x08 // mask bit 3
|
|
1041 |
#define GET_V_GCI_MR(R) (__u8)((R & M_GCI_MR) >> 3)
|
|
1042 |
|
|
1043 |
#define M_GCI_RX 0x10 // mask bit 4
|
|
1044 |
#define GET_V_GCI_RX(R) (__u8)((R & M_GCI_RX) >> 4)
|
|
1045 |
|
|
1046 |
#define M_GCI_ABO 0x20 // mask bit 5
|
|
1047 |
#define GET_V_GCI_ABO(R) (__u8)((R & M_GCI_ABO) >> 5)
|
|
1048 |
|
|
1049 |
|
|
1050 |
#define R_GCI_CFG1 0x2A // register address, write only
|
|
1051 |
#define M_GCI_SL 0x1F // mask bits 0..4
|
|
1052 |
#define SET_V_GCI_SL(R,V) (R = (__u8)((R & (__u8)(M_GCI_SL ^ 0xFF)) | (__u8)(V & 0x1F)))
|
|
1053 |
#define GET_V_GCI_SL(R) (__u8)(R & M_GCI_SL)
|
|
1054 |
|
|
1055 |
|
|
1056 |
#define R_MON_RX 0x2A // register address, read only
|
|
1057 |
#define M_MON_RX 0xFF // mask bits 0..7
|
|
1058 |
#define GET_V_MON_RX(R) (__u8)(R & M_MON_RX)
|
|
1059 |
|
|
1060 |
|
|
1061 |
#define R_MON_TX 0x2B // register address, write only
|
|
1062 |
#define M_MON_TX 0xFF // mask bits 0..7
|
|
1063 |
#define SET_V_MON_TX(R,V) (R = (__u8)((R & (__u8)(M_MON_TX ^ 0xFF)) | (__u8)V))
|
|
1064 |
#define GET_V_MON_TX(R) (__u8)(R & M_MON_TX)
|
|
1065 |
|
|
1066 |
|
|
1067 |
#define A_SU_WR_STA 0x30 // register address, write only
|
|
1068 |
#define M_SU_SET_STA 0x0F // mask bits 0..3
|
|
1069 |
#define SET_V_SU_SET_STA(R,V) (R = (__u8)((R & (__u8)(M_SU_SET_STA ^ 0xFF)) | (__u8)(V & 0x0F)))
|
|
1070 |
#define GET_V_SU_SET_STA(R) (__u8)(R & M_SU_SET_STA)
|
|
1071 |
|
|
1072 |
#define M_SU_LD_STA 0x10 // mask bit 4
|
|
1073 |
#define SET_V_SU_LD_STA(R,V) (R = (__u8)((R & (__u8)(M_SU_LD_STA ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
|
|
1074 |
#define GET_V_SU_LD_STA(R) (__u8)((R & M_SU_LD_STA) >> 4)
|
|
1075 |
|
|
1076 |
#define M_SU_ACT 0x60 // mask bits 5..6
|
|
1077 |
#define SET_V_SU_ACT(R,V) (R = (__u8)((R & (__u8)(M_SU_ACT ^ 0xFF)) | (__u8)((V & 0x03) << 5)))
|
|
1078 |
#define GET_V_SU_ACT(R) (__u8)((R & M_SU_ACT) >> 5)
|
|
1079 |
|
|
1080 |
#define M_SU_SET_G2_G3 0x80 // mask bit 7
|
|
1081 |
#define SET_V_SU_SET_G2_G3(R,V) (R = (__u8)((R & (__u8)(M_SU_SET_G2_G3 ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
1082 |
#define GET_V_SU_SET_G2_G3(R) (__u8)((R & M_SU_SET_G2_G3) >> 7)
|
|
1083 |
|
|
1084 |
|
|
1085 |
#define A_SU_RD_STA 0x30 // register address, read only
|
|
1086 |
#define M_SU_STA 0x0F // mask bits 0..3
|
|
1087 |
#define GET_V_SU_STA(R) (__u8)(R & M_SU_STA)
|
|
1088 |
|
|
1089 |
#define M_SU_FR_SYNC 0x10 // mask bit 4
|
|
1090 |
#define GET_V_SU_FR_SYNC(R) (__u8)((R & M_SU_FR_SYNC) >> 4)
|
|
1091 |
|
|
1092 |
#define M_SU_T2_EXP 0x20 // mask bit 5
|
|
1093 |
#define GET_V_SU_T2_EXP(R) (__u8)((R & M_SU_T2_EXP) >> 5)
|
|
1094 |
|
|
1095 |
#define M_SU_INFO0 0x40 // mask bit 6
|
|
1096 |
#define GET_V_SU_INFO0(R) (__u8)((R & M_SU_INFO0) >> 6)
|
|
1097 |
|
|
1098 |
#define M_G2_G3 0x80 // mask bit 7
|
|
1099 |
#define GET_V_G2_G3(R) (__u8)((R & M_G2_G3) >> 7)
|
|
1100 |
|
|
1101 |
|
|
1102 |
#define A_SU_CTRL0 0x31 // register address, write only
|
|
1103 |
#define M_B1_TX_EN 0x01 // mask bit 0
|
|
1104 |
#define SET_V_B1_TX_EN(R,V) (R = (__u8)((R & (__u8)(M_B1_TX_EN ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
1105 |
#define GET_V_B1_TX_EN(R) (__u8)(R & M_B1_TX_EN)
|
|
1106 |
|
|
1107 |
#define M_B2_TX_EN 0x02 // mask bit 1
|
|
1108 |
#define SET_V_B2_TX_EN(R,V) (R = (__u8)((R & (__u8)(M_B2_TX_EN ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
|
|
1109 |
#define GET_V_B2_TX_EN(R) (__u8)((R & M_B2_TX_EN) >> 1)
|
|
1110 |
|
|
1111 |
#define M_SU_MD 0x04 // mask bit 2
|
|
1112 |
#define SET_V_SU_MD(R,V) (R = (__u8)((R & (__u8)(M_SU_MD ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
|
|
1113 |
#define GET_V_SU_MD(R) (__u8)((R & M_SU_MD) >> 2)
|
|
1114 |
|
|
1115 |
#define M_ST_D_LPRIO 0x08 // mask bit 3
|
|
1116 |
#define SET_V_ST_D_LPRIO(R,V) (R = (__u8)((R & (__u8)(M_ST_D_LPRIO ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
1117 |
#define GET_V_ST_D_LPRIO(R) (__u8)((R & M_ST_D_LPRIO) >> 3)
|
|
1118 |
|
|
1119 |
#define M_ST_SQ_EN 0x10 // mask bit 4
|
|
1120 |
#define SET_V_ST_SQ_EN(R,V) (R = (__u8)((R & (__u8)(M_ST_SQ_EN ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
|
|
1121 |
#define GET_V_ST_SQ_EN(R) (__u8)((R & M_ST_SQ_EN) >> 4)
|
|
1122 |
|
|
1123 |
#define M_SU_TST_SIG 0x20 // mask bit 5
|
|
1124 |
#define SET_V_SU_TST_SIG(R,V) (R = (__u8)((R & (__u8)(M_SU_TST_SIG ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
|
|
1125 |
#define GET_V_SU_TST_SIG(R) (__u8)((R & M_SU_TST_SIG) >> 5)
|
|
1126 |
|
|
1127 |
#define M_ST_PU_CTRL 0x40 // mask bit 6
|
|
1128 |
#define SET_V_ST_PU_CTRL(R,V) (R = (__u8)((R & (__u8)(M_ST_PU_CTRL ^ 0xFF)) | (__u8)((V & 0x01) << 6)))
|
|
1129 |
#define GET_V_ST_PU_CTRL(R) (__u8)((R & M_ST_PU_CTRL) >> 6)
|
|
1130 |
|
|
1131 |
#define M_SU_STOP 0x80 // mask bit 7
|
|
1132 |
#define SET_V_SU_STOP(R,V) (R = (__u8)((R & (__u8)(M_SU_STOP ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
1133 |
#define GET_V_SU_STOP(R) (__u8)((R & M_SU_STOP) >> 7)
|
|
1134 |
|
|
1135 |
|
|
1136 |
#define A_SU_DLYL 0x31 // register address, read only
|
|
1137 |
#define M_SU_DLYL 0x1F // mask bits 0..4
|
|
1138 |
#define GET_V_SU_DLYL(R) (__u8)(R & M_SU_DLYL)
|
|
1139 |
|
|
1140 |
|
|
1141 |
#define A_SU_CTRL1 0x32 // register address, write only
|
|
1142 |
#define M_G2_G3_EN 0x01 // mask bit 0
|
|
1143 |
#define SET_V_G2_G3_EN(R,V) (R = (__u8)((R & (__u8)(M_G2_G3_EN ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
1144 |
#define GET_V_G2_G3_EN(R) (__u8)(R & M_G2_G3_EN)
|
|
1145 |
|
|
1146 |
#define M_D_RES 0x04 // mask bit 2
|
|
1147 |
#define SET_V_D_RES(R,V) (R = (__u8)((R & (__u8)(M_D_RES ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
|
|
1148 |
#define GET_V_D_RES(R) (__u8)((R & M_D_RES) >> 2)
|
|
1149 |
|
|
1150 |
#define M_ST_E_IGNO 0x08 // mask bit 3
|
|
1151 |
#define SET_V_ST_E_IGNO(R,V) (R = (__u8)((R & (__u8)(M_ST_E_IGNO ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
1152 |
#define GET_V_ST_E_IGNO(R) (__u8)((R & M_ST_E_IGNO) >> 3)
|
|
1153 |
|
|
1154 |
#define M_ST_E_LO 0x10 // mask bit 4
|
|
1155 |
#define SET_V_ST_E_LO(R,V) (R = (__u8)((R & (__u8)(M_ST_E_LO ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
|
|
1156 |
#define GET_V_ST_E_LO(R) (__u8)((R & M_ST_E_LO) >> 4)
|
|
1157 |
|
|
1158 |
#define M_BAC_D 0x40 // mask bit 6
|
|
1159 |
#define SET_V_BAC_D(R,V) (R = (__u8)((R & (__u8)(M_BAC_D ^ 0xFF)) | (__u8)((V & 0x01) << 6)))
|
|
1160 |
#define GET_V_BAC_D(R) (__u8)((R & M_BAC_D) >> 6)
|
|
1161 |
|
|
1162 |
#define M_B12_SWAP 0x80 // mask bit 7
|
|
1163 |
#define SET_V_B12_SWAP(R,V) (R = (__u8)((R & (__u8)(M_B12_SWAP ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
1164 |
#define GET_V_B12_SWAP(R) (__u8)((R & M_B12_SWAP) >> 7)
|
|
1165 |
|
|
1166 |
|
|
1167 |
#define A_SU_DLYH 0x32 // register address, read only
|
|
1168 |
#define M_SU_DLYH 0x1F // mask bits 0..4
|
|
1169 |
#define GET_V_SU_DLYH(R) (__u8)(R & M_SU_DLYH)
|
|
1170 |
|
|
1171 |
|
|
1172 |
#define A_SU_CTRL2 0x33 // register address, write only
|
|
1173 |
#define M_B1_RX_EN 0x01 // mask bit 0
|
|
1174 |
#define SET_V_B1_RX_EN(R,V) (R = (__u8)((R & (__u8)(M_B1_RX_EN ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
1175 |
#define GET_V_B1_RX_EN(R) (__u8)(R & M_B1_RX_EN)
|
|
1176 |
|
|
1177 |
#define M_B2_RX_EN 0x02 // mask bit 1
|
|
1178 |
#define SET_V_B2_RX_EN(R,V) (R = (__u8)((R & (__u8)(M_B2_RX_EN ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
|
|
1179 |
#define GET_V_B2_RX_EN(R) (__u8)((R & M_B2_RX_EN) >> 1)
|
|
1180 |
|
|
1181 |
#define M_MS_SSYNC2 0x04 // mask bit 2
|
|
1182 |
#define SET_V_MS_SSYNC2(R,V) (R = (__u8)((R & (__u8)(M_MS_SSYNC2 ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
|
|
1183 |
#define GET_V_MS_SSYNC2(R) (__u8)((R & M_MS_SSYNC2) >> 2)
|
|
1184 |
|
|
1185 |
#define M_BAC_S_SEL 0x08 // mask bit 3
|
|
1186 |
#define SET_V_BAC_S_SEL(R,V) (R = (__u8)((R & (__u8)(M_BAC_S_SEL ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
1187 |
#define GET_V_BAC_S_SEL(R) (__u8)((R & M_BAC_S_SEL) >> 3)
|
|
1188 |
|
|
1189 |
#define M_SU_SYNC_NT 0x10 // mask bit 4
|
|
1190 |
#define SET_V_SU_SYNC_NT(R,V) (R = (__u8)((R & (__u8)(M_SU_SYNC_NT ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
|
|
1191 |
#define GET_V_SU_SYNC_NT(R) (__u8)((R & M_SU_SYNC_NT) >> 4)
|
|
1192 |
|
|
1193 |
#define M_SU_2KHZ 0x20 // mask bit 5
|
|
1194 |
#define SET_V_SU_2KHZ(R,V) (R = (__u8)((R & (__u8)(M_SU_2KHZ ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
|
|
1195 |
#define GET_V_SU_2KHZ(R) (__u8)((R & M_SU_2KHZ) >> 5)
|
|
1196 |
|
|
1197 |
#define M_SU_TRI 0x40 // mask bit 6
|
|
1198 |
#define SET_V_SU_TRI(R,V) (R = (__u8)((R & (__u8)(M_SU_TRI ^ 0xFF)) | (__u8)((V & 0x01) << 6)))
|
|
1199 |
#define GET_V_SU_TRI(R) (__u8)((R & M_SU_TRI) >> 6)
|
|
1200 |
|
|
1201 |
#define M_SU_EXCHG 0x80 // mask bit 7
|
|
1202 |
#define SET_V_SU_EXCHG(R,V) (R = (__u8)((R & (__u8)(M_SU_EXCHG ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
1203 |
#define GET_V_SU_EXCHG(R) (__u8)((R & M_SU_EXCHG) >> 7)
|
|
1204 |
|
|
1205 |
|
|
1206 |
#define A_MS_TX 0x34 // register address, write only
|
|
1207 |
#define M_MS_TX 0x0F // mask bits 0..3
|
|
1208 |
#define SET_V_MS_TX(R,V) (R = (__u8)((R & (__u8)(M_MS_TX ^ 0xFF)) | (__u8)(V & 0x0F)))
|
|
1209 |
#define GET_V_MS_TX(R) (__u8)(R & M_MS_TX)
|
|
1210 |
|
|
1211 |
#define M_UP_S_TX 0x40 // mask bit 6
|
|
1212 |
#define SET_V_UP_S_TX(R,V) (R = (__u8)((R & (__u8)(M_UP_S_TX ^ 0xFF)) | (__u8)((V & 0x01) << 6)))
|
|
1213 |
#define GET_V_UP_S_TX(R) (__u8)((R & M_UP_S_TX) >> 6)
|
|
1214 |
|
|
1215 |
|
|
1216 |
#define A_MS_RX 0x34 // register address, read only
|
|
1217 |
#define M_MS_RX 0x0F // mask bits 0..3
|
|
1218 |
#define GET_V_MS_RX(R) (__u8)(R & M_MS_RX)
|
|
1219 |
|
|
1220 |
#define M_MS_RX_RDY 0x10 // mask bit 4
|
|
1221 |
#define GET_V_MS_RX_RDY(R) (__u8)((R & M_MS_RX_RDY) >> 4)
|
|
1222 |
|
|
1223 |
#define M_UP_S_RX 0x40 // mask bit 6
|
|
1224 |
#define GET_V_UP_S_RX(R) (__u8)((R & M_UP_S_RX) >> 6)
|
|
1225 |
|
|
1226 |
#define M_MS_TX_RDY 0x80 // mask bit 7
|
|
1227 |
#define GET_V_MS_TX_RDY(R) (__u8)((R & M_MS_TX_RDY) >> 7)
|
|
1228 |
|
|
1229 |
|
|
1230 |
#define A_ST_CTRL3 0x35 // register address, write only
|
|
1231 |
#define M_ST_SEL 0x01 // mask bit 0
|
|
1232 |
#define SET_V_ST_SEL(R,V) (R = (__u8)((R & (__u8)(M_ST_SEL ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
1233 |
#define GET_V_ST_SEL(R) (__u8)(R & M_ST_SEL)
|
|
1234 |
|
|
1235 |
#define M_ST_PULSE 0xFE // mask bits 1..7
|
|
1236 |
#define SET_V_ST_PULSE(R,V) (R = (__u8)((R & (__u8)(M_ST_PULSE ^ 0xFF)) | (__u8)((V & 0x7F) << 1)))
|
|
1237 |
#define GET_V_ST_PULSE(R) (__u8)((R & M_ST_PULSE) >> 1)
|
|
1238 |
|
|
1239 |
|
|
1240 |
#define A_UP_CTRL3 0x35 // register address, write only
|
|
1241 |
#define M_UP_SEL 0x01 // mask bit 0
|
|
1242 |
#define SET_V_UP_SEL(R,V) (R = (__u8)((R & (__u8)(M_UP_SEL ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
1243 |
#define GET_V_UP_SEL(R) (__u8)(R & M_UP_SEL)
|
|
1244 |
|
|
1245 |
#define M_UP_VIO 0x02 // mask bit 1
|
|
1246 |
#define SET_V_UP_VIO(R,V) (R = (__u8)((R & (__u8)(M_UP_VIO ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
|
|
1247 |
#define GET_V_UP_VIO(R) (__u8)((R & M_UP_VIO) >> 1)
|
|
1248 |
|
|
1249 |
#define M_UP_DC_STR 0x04 // mask bit 2
|
|
1250 |
#define SET_V_UP_DC_STR(R,V) (R = (__u8)((R & (__u8)(M_UP_DC_STR ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
|
|
1251 |
#define GET_V_UP_DC_STR(R) (__u8)((R & M_UP_DC_STR) >> 2)
|
|
1252 |
|
|
1253 |
#define M_UP_DC_OFF 0x08 // mask bit 3
|
|
1254 |
#define SET_V_UP_DC_OFF(R,V) (R = (__u8)((R & (__u8)(M_UP_DC_OFF ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
1255 |
#define GET_V_UP_DC_OFF(R) (__u8)((R & M_UP_DC_OFF) >> 3)
|
|
1256 |
|
|
1257 |
#define M_UP_RPT_PAT 0x10 // mask bit 4
|
|
1258 |
#define SET_V_UP_RPT_PAT(R,V) (R = (__u8)((R & (__u8)(M_UP_RPT_PAT ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
|
|
1259 |
#define GET_V_UP_RPT_PAT(R) (__u8)((R & M_UP_RPT_PAT) >> 4)
|
|
1260 |
|
|
1261 |
#define M_UP_SCRM_MD 0x20 // mask bit 5
|
|
1262 |
#define SET_V_UP_SCRM_MD(R,V) (R = (__u8)((R & (__u8)(M_UP_SCRM_MD ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
|
|
1263 |
#define GET_V_UP_SCRM_MD(R) (__u8)((R & M_UP_SCRM_MD) >> 5)
|
|
1264 |
|
|
1265 |
#define M_UP_SCRM_TX_OFF 0x40 // mask bit 6
|
|
1266 |
#define SET_V_UP_SCRM_TX_OFF(R,V) (R = (__u8)((R & (__u8)(M_UP_SCRM_TX_OFF ^ 0xFF)) | (__u8)((V & 0x01) << 6)))
|
|
1267 |
#define GET_V_UP_SCRM_TX_OFF(R) (__u8)((R & M_UP_SCRM_TX_OFF) >> 6)
|
|
1268 |
|
|
1269 |
#define M_UP_SCRM_RX_OFF 0x80 // mask bit 7
|
|
1270 |
#define SET_V_UP_SCRM_RX_OFF(R,V) (R = (__u8)((R & (__u8)(M_UP_SCRM_RX_OFF ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
1271 |
#define GET_V_UP_SCRM_RX_OFF(R) (__u8)((R & M_UP_SCRM_RX_OFF) >> 7)
|
|
1272 |
|
|
1273 |
|
|
1274 |
#define A_SU_STA 0x35 // register address, read only
|
|
1275 |
#define M_ST_D_HPRIO9 0x01 // mask bit 0
|
|
1276 |
#define GET_V_ST_D_HPRIO9(R) (__u8)(R & M_ST_D_HPRIO9)
|
|
1277 |
|
|
1278 |
#define M_ST_D_LPRIO11 0x02 // mask bit 1
|
|
1279 |
#define GET_V_ST_D_LPRIO11(R) (__u8)((R & M_ST_D_LPRIO11) >> 1)
|
|
1280 |
|
|
1281 |
#define M_ST_D_CONT 0x04 // mask bit 2
|
|
1282 |
#define GET_V_ST_D_CONT(R) (__u8)((R & M_ST_D_CONT) >> 2)
|
|
1283 |
|
|
1284 |
#define M_ST_D_ACT 0x08 // mask bit 3
|
|
1285 |
#define GET_V_ST_D_ACT(R) (__u8)((R & M_ST_D_ACT) >> 3)
|
|
1286 |
|
|
1287 |
#define M_SU_AF0 0x80 // mask bit 7
|
|
1288 |
#define GET_V_SU_AF0(R) (__u8)((R & M_SU_AF0) >> 7)
|
|
1289 |
|
|
1290 |
|
|
1291 |
#define A_MS_DF 0x36 // register address, write only
|
|
1292 |
#define M_BAC_NINV 0x01 // mask bit 0
|
|
1293 |
#define SET_V_BAC_NINV(R,V) (R = (__u8)((R & (__u8)(M_BAC_NINV ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
1294 |
#define GET_V_BAC_NINV(R) (__u8)(R & M_BAC_NINV)
|
|
1295 |
|
|
1296 |
#define M_SG_AB_INV 0x02 // mask bit 1
|
|
1297 |
#define SET_V_SG_AB_INV(R,V) (R = (__u8)((R & (__u8)(M_SG_AB_INV ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
|
|
1298 |
#define GET_V_SG_AB_INV(R) (__u8)((R & M_SG_AB_INV) >> 1)
|
|
1299 |
|
|
1300 |
#define M_SQ_T_SRC 0x04 // mask bit 2
|
|
1301 |
#define SET_V_SQ_T_SRC(R,V) (R = (__u8)((R & (__u8)(M_SQ_T_SRC ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
|
|
1302 |
#define GET_V_SQ_T_SRC(R) (__u8)((R & M_SQ_T_SRC) >> 2)
|
|
1303 |
|
|
1304 |
#define M_M_S_SRC 0x08 // mask bit 3
|
|
1305 |
#define SET_V_M_S_SRC(R,V) (R = (__u8)((R & (__u8)(M_M_S_SRC ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
1306 |
#define GET_V_M_S_SRC(R) (__u8)((R & M_M_S_SRC) >> 3)
|
|
1307 |
|
|
1308 |
#define M_SQ_T_DST 0x10 // mask bit 4
|
|
1309 |
#define SET_V_SQ_T_DST(R,V) (R = (__u8)((R & (__u8)(M_SQ_T_DST ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
|
|
1310 |
#define GET_V_SQ_T_DST(R) (__u8)((R & M_SQ_T_DST) >> 4)
|
|
1311 |
|
|
1312 |
#define M_SU_RX_VAL 0x20 // mask bit 5
|
|
1313 |
#define SET_V_SU_RX_VAL(R,V) (R = (__u8)((R & (__u8)(M_SU_RX_VAL ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
|
|
1314 |
#define GET_V_SU_RX_VAL(R) (__u8)((R & M_SU_RX_VAL) >> 5)
|
|
1315 |
|
|
1316 |
|
|
1317 |
#define A_SU_CLK_DLY 0x37 // register address, write only
|
|
1318 |
#define M_SU_CLK_DLY 0x0F // mask bits 0..3
|
|
1319 |
#define SET_V_SU_CLK_DLY(R,V) (R = (__u8)((R & (__u8)(M_SU_CLK_DLY ^ 0xFF)) | (__u8)(V & 0x0F)))
|
|
1320 |
#define GET_V_SU_CLK_DLY(R) (__u8)(R & M_SU_CLK_DLY)
|
|
1321 |
|
|
1322 |
#define M_ST_SMPL 0x70 // mask bits 4..6
|
|
1323 |
#define SET_V_ST_SMPL(R,V) (R = (__u8)((R & (__u8)(M_ST_SMPL ^ 0xFF)) | (__u8)((V & 0x07) << 4)))
|
|
1324 |
#define GET_V_ST_SMPL(R) (__u8)((R & M_ST_SMPL) >> 4)
|
|
1325 |
|
|
1326 |
|
|
1327 |
#define R_PWM0 0x38 // register address, write only
|
|
1328 |
#define M_PWM0 0xFF // mask bits 0..7
|
|
1329 |
#define SET_V_PWM0(R,V) (R = (__u8)((R & (__u8)(M_PWM0 ^ 0xFF)) | (__u8)V))
|
|
1330 |
#define GET_V_PWM0(R) (__u8)(R & M_PWM0)
|
|
1331 |
|
|
1332 |
|
|
1333 |
#define R_PWM1 0x39 // register address, write only
|
|
1334 |
#define M_PWM1 0xFF // mask bits 0..7
|
|
1335 |
#define SET_V_PWM1(R,V) (R = (__u8)((R & (__u8)(M_PWM1 ^ 0xFF)) | (__u8)V))
|
|
1336 |
#define GET_V_PWM1(R) (__u8)(R & M_PWM1)
|
|
1337 |
|
|
1338 |
|
|
1339 |
#define A_B1_TX 0x3C // register address, write only
|
|
1340 |
#define M_B1_TX 0xFF // mask bits 0..7
|
|
1341 |
#define SET_V_B1_TX(R,V) (R = (__u8)((R & (__u8)(M_B1_TX ^ 0xFF)) | (__u8)V))
|
|
1342 |
#define GET_V_B1_TX(R) (__u8)(R & M_B1_TX)
|
|
1343 |
|
|
1344 |
|
|
1345 |
#define A_B1_RX 0x3C // register address, read only
|
|
1346 |
#define M_B1_RX 0xFF // mask bits 0..7
|
|
1347 |
#define GET_V_B1_RX(R) (__u8)(R & M_B1_RX)
|
|
1348 |
|
|
1349 |
|
|
1350 |
#define A_B2_TX 0x3D // register address, write only
|
|
1351 |
#define M_B2_TX 0xFF // mask bits 0..7
|
|
1352 |
#define SET_V_B2_TX(R,V) (R = (__u8)((R & (__u8)(M_B2_TX ^ 0xFF)) | (__u8)V))
|
|
1353 |
#define GET_V_B2_TX(R) (__u8)(R & M_B2_TX)
|
|
1354 |
|
|
1355 |
|
|
1356 |
#define A_B2_RX 0x3D // register address, read only
|
|
1357 |
#define M_B2_RX 0xFF // mask bits 0..7
|
|
1358 |
#define GET_V_B2_RX(R) (__u8)(R & M_B2_RX)
|
|
1359 |
|
|
1360 |
|
|
1361 |
#define A_D_TX 0x3E // register address, write only
|
|
1362 |
#define M_D_TX_S 0x01 // mask bit 0
|
|
1363 |
#define SET_V_D_TX_S(R,V) (R = (__u8)((R & (__u8)(M_D_TX_S ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
1364 |
#define GET_V_D_TX_S(R) (__u8)(R & M_D_TX_S)
|
|
1365 |
|
|
1366 |
#define M_D_TX_BAC 0x20 // mask bit 5
|
|
1367 |
#define SET_V_D_TX_BAC(R,V) (R = (__u8)((R & (__u8)(M_D_TX_BAC ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
|
|
1368 |
#define GET_V_D_TX_BAC(R) (__u8)((R & M_D_TX_BAC) >> 5)
|
|
1369 |
|
|
1370 |
#define M_D_TX 0xC0 // mask bits 6..7
|
|
1371 |
#define SET_V_D_TX(R,V) (R = (__u8)((R & (__u8)(M_D_TX ^ 0xFF)) | (__u8)((V & 0x03) << 6)))
|
|
1372 |
#define GET_V_D_TX(R) (__u8)((R & M_D_TX) >> 6)
|
|
1373 |
|
|
1374 |
|
|
1375 |
#define A_D_RX 0x3E // register address, read only
|
|
1376 |
#define M_D_RX_S 0x01 // mask bit 0
|
|
1377 |
#define GET_V_D_RX_S(R) (__u8)(R & M_D_RX_S)
|
|
1378 |
|
|
1379 |
#define M_D_RX_AB 0x10 // mask bit 4
|
|
1380 |
#define GET_V_D_RX_AB(R) (__u8)((R & M_D_RX_AB) >> 4)
|
|
1381 |
|
|
1382 |
#define M_D_RX_SG 0x20 // mask bit 5
|
|
1383 |
#define GET_V_D_RX_SG(R) (__u8)((R & M_D_RX_SG) >> 5)
|
|
1384 |
|
|
1385 |
#define M_D_RX 0xC0 // mask bits 6..7
|
|
1386 |
#define GET_V_D_RX(R) (__u8)((R & M_D_RX) >> 6)
|
|
1387 |
|
|
1388 |
|
|
1389 |
#define A_E_RX 0x3F // register address, read only
|
|
1390 |
#define M_E_RX_S 0x01 // mask bit 0
|
|
1391 |
#define GET_V_E_RX_S(R) (__u8)(R & M_E_RX_S)
|
|
1392 |
|
|
1393 |
#define M_E_RX_AB 0x10 // mask bit 4
|
|
1394 |
#define GET_V_E_RX_AB(R) (__u8)((R & M_E_RX_AB) >> 4)
|
|
1395 |
|
|
1396 |
#define M_E_RX_SG 0x20 // mask bit 5
|
|
1397 |
#define GET_V_E_RX_SG(R) (__u8)((R & M_E_RX_SG) >> 5)
|
|
1398 |
|
|
1399 |
#define M_E_RX 0xC0 // mask bits 6..7
|
|
1400 |
#define GET_V_E_RX(R) (__u8)((R & M_E_RX) >> 6)
|
|
1401 |
|
|
1402 |
|
|
1403 |
#define A_BAC_S_TX 0x3F // register address, write only
|
|
1404 |
#define M_S_TX 0x01 // mask bit 0
|
|
1405 |
#define SET_V_S_TX(R,V) (R = (__u8)((R & (__u8)(M_S_TX ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
1406 |
#define GET_V_S_TX(R) (__u8)(R & M_S_TX)
|
|
1407 |
|
|
1408 |
#define M_BAC_TX 0x20 // mask bit 5
|
|
1409 |
#define SET_V_BAC_TX(R,V) (R = (__u8)((R & (__u8)(M_BAC_TX ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
|
|
1410 |
#define GET_V_BAC_TX(R) (__u8)((R & M_BAC_TX) >> 5)
|
|
1411 |
|
|
1412 |
|
|
1413 |
#define R_GPIO_OUT1 0x40 // register address, write only
|
|
1414 |
#define M_GPIO_OUT8 0x01 // mask bit 0
|
|
1415 |
#define SET_V_GPIO_OUT8(R,V) (R = (__u8)((R & (__u8)(M_GPIO_OUT8 ^ 0xFF)) | (__u8)(V & 0x01)))
|
|
1416 |
#define GET_V_GPIO_OUT8(R) (__u8)(R & M_GPIO_OUT8)
|
|
1417 |
|
|
1418 |
#define M_GPIO_OUT9 0x02 // mask bit 1
|
|
1419 |
#define SET_V_GPIO_OUT9(R,V) (R = (__u8)((R & (__u8)(M_GPIO_OUT9 ^ 0xFF)) | (__u8)((V & 0x01) << 1)))
|
|
1420 |
#define GET_V_GPIO_OUT9(R) (__u8)((R & M_GPIO_OUT9) >> 1)
|
|
1421 |
|
|
1422 |
#define M_GPIO_OUT10 0x04 // mask bit 2
|
|
1423 |
#define SET_V_GPIO_OUT10(R,V) (R = (__u8)((R & (__u8)(M_GPIO_OUT10 ^ 0xFF)) | (__u8)((V & 0x01) << 2)))
|
|
1424 |
#define GET_V_GPIO_OUT10(R) (__u8)((R & M_GPIO_OUT10) >> 2)
|
|
1425 |
|
|
1426 |
#define M_GPIO_OUT11 0x08 // mask bit 3
|
|
1427 |
#define SET_V_GPIO_OUT11(R,V) (R = (__u8)((R & (__u8)(M_GPIO_OUT11 ^ 0xFF)) | (__u8)((V & 0x01) << 3)))
|
|
1428 |
#define GET_V_GPIO_OUT11(R) (__u8)((R & M_GPIO_OUT11) >> 3)
|
|
1429 |
|
|
1430 |
#define M_GPIO_OUT12 0x10 // mask bit 4
|
|
1431 |
#define SET_V_GPIO_OUT12(R,V) (R = (__u8)((R & (__u8)(M_GPIO_OUT12 ^ 0xFF)) | (__u8)((V & 0x01) << 4)))
|
|
1432 |
#define GET_V_GPIO_OUT12(R) (__u8)((R & M_GPIO_OUT12) >> 4)
|
|
1433 |
|
|
1434 |
#define M_GPIO_OUT13 0x20 // mask bit 5
|
|
1435 |
#define SET_V_GPIO_OUT13(R,V) (R = (__u8)((R & (__u8)(M_GPIO_OUT13 ^ 0xFF)) | (__u8)((V & 0x01) << 5)))
|
|
1436 |
#define GET_V_GPIO_OUT13(R) (__u8)((R & M_GPIO_OUT13) >> 5)
|
|
1437 |
|
|
1438 |
#define M_GPIO_OUT14 0x40 // mask bit 6
|
|
1439 |
#define SET_V_GPIO_OUT14(R,V) (R = (__u8)((R & (__u8)(M_GPIO_OUT14 ^ 0xFF)) | (__u8)((V & 0x01) << 6)))
|
|
1440 |
#define GET_V_GPIO_OUT14(R) (__u8)((R & M_GPIO_OUT14) >> 6)
|
|
1441 |
|
|
1442 |
#define M_GPIO_OUT15 0x80 // mask bit 7
|
|
1443 |
#define SET_V_GPIO_OUT15(R,V) (R = (__u8)((R & (__u8)(M_GPIO_OUT15 ^ 0xFF)) | (__u8)((V & 0x01) << 7)))
|
|
1444 |
#define GET_V_GPIO_OUT15(R) (__u8)((R & M_GPIO_OUT15) >> 7)
|
|
1445 |
|
