GsmDevelBoard » History » Version 2
laforge, 02/19/2016 10:48 PM
add requirements section
1 | 1 | laforge | |
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2 | 2 | laforge | == Requirements for the GSM MS side == |
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4 | * transmit and receive in one TS every frame |
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5 | * retune Rx and Tx according to hopping sequence for every frame |
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6 | * synchronize carrier clock, bitclock and frame with BTS |
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7 | |||
8 | == Requirements for a GSM scanner == |
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9 | |||
10 | * two independent receivers, one on MS-Rx, the other on BTS-Rx side |
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11 | * ability to start decoding at some point (PCH/AGCH/SDCCH) and then follow a given hopping sequence (MAIO) for one TCH |
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12 | * ability to decrypt A51/A52 with user-provided Kc |
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13 | * Jammer: possibly transmitting interference in the Tx slices of the victim |
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14 | * synchronize carrier clock, bitclock and frame with BTS |
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15 | |||
16 | === Possible implementation === |
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17 | |||
18 | * two TRF6151 in pure Rx configuration |
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19 | * one for MS-Rx side |
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20 | * other one for MS-Tx side |
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21 | * two TWL3025 in pure Rx configuration |
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22 | * both TWL3025 BSP permanently in downlink mode (I/Q samples) |
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23 | * we get 2*( 2*16*270k) bps serial samples (7.33Mbps) input signal |
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24 | * connect those two serial sample streams to CPU+DSP (blackfin?) |
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25 | * forward demodulated/decoded samples to PC |
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26 | |||
27 | == Requirements for a GSM BTS == |
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28 | |||
29 | * tune MS-Rx side to MS-Tx frequency |
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30 | * tune MS-Tx side to MS-Rx frequency |
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31 | * continuous Rx and Tx in all timeslots on one ARFCN |
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32 | * ability to determine timing advance of Uplink frames |
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33 | |||
34 | === Possible implementation === |
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35 | |||
36 | * Use two independent TRF6151 frontends one for uplink, one for downlink |
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37 | * First TRF6151 will generate 26MHz and respect AFC from TWL3025 |
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38 | * Second TRF6151 will use 'external VTXCO' configuration from 26MHz clock |
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39 | 1 | laforge | |
40 | == Internal Interfaces == |
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41 | |||
42 | In this board, we have a number of interesting internal interfaces. |
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43 | |||
44 | It would be great if we could somehow tap/hook our own processor into those interfaces. |
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45 | |||
46 | === TWL3025 BSP === |
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47 | |||
48 | This is a SPI port with read/write access to all TWL3025 internal registers. However, in case of downlink Rx operation, the burst |
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49 | data is transferred over this port (which needs 8.66Mbps of the 13Mbps bandwidth). It is clocked by CLK13M |
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50 | |||
51 | This typically connects to the Calypso BSP. |
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52 | |||
53 | === TWL3025 USP === |
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54 | |||
55 | This is a generic SPI port for read/write to all TWL3025 internal registers. It is clocked by CLK13M |
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56 | |||
57 | === TWL3025 TSP === |
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58 | |||
59 | The Time Serial Port is clocked by CLK13M/2 and is a pure input port, i.e. a Frame and a Data-In line are sufficient. |
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60 | |||
61 | This typically connects to the Calypso TPU. |
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62 | |||
63 | This interface is used for sequencing the Rx/Tx operation of the baseband interface. |
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64 | |||
65 | === TRF6151C TSP === |
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66 | |||
67 | This is a serial interface with strobe (not chip select). |
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68 | |||
69 | It is mostly used to configure the PLL, PGA Gain and power of the transceiver. |
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70 | |||
71 | This typically connects to the Calypso TSP/TPU |