HardwareCalypso » History » Version 6
laforge, 02/19/2016 10:48 PM
| 1 | 5 | laforge | [[PageOutline]] |
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| 2 | 1 | laforge | = Calypso Digital Baseband = |
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| 4 | The Calypso Digital Base Band chip is a popular DBB implementation for inexpensive feature phones. |
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| 6 | 5 | laforge | The register-level manuals seem to have leaked at some point and are available from cryptome.org |
| 7 | 6 | laforge | at http://cryptome.org/ti-calypso2.pdf and http://cryptome.org/ti-calypso1.pdf |
| 8 | 5 | laforge | |
| 9 | 1 | laforge | == Variants == |
| 10 | * Calypso G2 C035 |
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| 11 | * Calypso G2 C035 Lite (D751749GHH) |
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| 12 | * Like C035, only 256kBytes of internal memory |
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| 13 | 2 | laforge | |
| 14 | 3 | laforge | == Memory Map == |
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| 16 | 4 | roh | * nCS0 0x0000'0000 ... 0x007f'ffff (C123: external NOR flash) |
| 17 | 3 | laforge | * nCS6 0x0080'0000 ... 0x00bf'ffff (internal SRAM, in case of calypso lite only 256kBytes) |
| 18 | * nCS1 0x0100'0000 ... 0x017f'ffff (C123: external SRAM) |
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| 19 | 2 | laforge | |
| 20 | == Integrated Peripherals == |
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| 22 | === I2C Controller === |
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| 23 | |||
| 24 | The controller has two oddities: |
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| 25 | * It assumes that the peripheral has an address byte. If your peripheral doesn't, you have to |
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| 26 | write the first byte into the address register and not the FIFO |
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| 27 | * You cannot under-fill the FIFO, i.e. if you write 8 bytes into the 16byte deep fifo, the controller |
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| 28 | will transmit 16 bytes rather than 8. Therefore, always limit the FIFO depth to your write size! |
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| 29 | More details about this can be seen at [wiki:CalypsoI2CFIFO] |
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| 30 | 5 | laforge | |
| 31 | === Timers === |
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| 32 | |||
| 33 | The timer input clock is not mentioned in the data sheet. It seems to be 13MHz / 32, i.e. 406.25kHz |
