HardwareCalypso » History » Version 7
laforge, 02/19/2016 10:48 PM
add more info about integrated peripherals
| 1 | 5 | laforge | [[PageOutline]] |
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| 2 | 1 | laforge | = Calypso Digital Baseband = |
| 3 | |||
| 4 | The Calypso Digital Base Band chip is a popular DBB implementation for inexpensive feature phones. |
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| 6 | 5 | laforge | The register-level manuals seem to have leaked at some point and are available from cryptome.org |
| 7 | 6 | laforge | at http://cryptome.org/ti-calypso2.pdf and http://cryptome.org/ti-calypso1.pdf |
| 8 | 5 | laforge | |
| 9 | 7 | laforge | |
| 10 | |||
| 11 | 1 | laforge | == Variants == |
| 12 | * Calypso G2 C035 |
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| 13 | * Calypso G2 C035 Lite (D751749GHH) |
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| 14 | * Like C035, only 256kBytes of internal memory |
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| 15 | 2 | laforge | |
| 16 | 3 | laforge | == Memory Map == |
| 17 | |||
| 18 | 4 | roh | * nCS0 0x0000'0000 ... 0x007f'ffff (C123: external NOR flash) |
| 19 | 3 | laforge | * nCS6 0x0080'0000 ... 0x00bf'ffff (internal SRAM, in case of calypso lite only 256kBytes) |
| 20 | * nCS1 0x0100'0000 ... 0x017f'ffff (C123: external SRAM) |
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| 21 | 2 | laforge | |
| 22 | == Integrated Peripherals == |
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| 23 | 7 | laforge | == Integrated Peripherals == |
| 24 | === TPU (Time Processing Unit) === |
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| 25 | * A programmable micro-engine clocked at GSM quarter-bit clock |
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| 26 | === MODEM UART === |
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| 27 | * The UART that is typically connected to a PC or the application processor in a smartphone |
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| 28 | === IRDA UART === |
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| 29 | * The UART that is either connected to IRDA or for diagnostics/programming |
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| 30 | === RIF (Radio Interface) === |
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| 31 | * Connects to the synchronous bi-directional BSP (Baseband Serial Port) |
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| 32 | === DPLL + clock block === |
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| 33 | * Generate clocks for DSP, ARM and all peripherals |
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| 34 | === GEA (GPRS Encryption Algorithm) === |
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| 35 | * Encrypts/Decrypts data according to the proprietary GEA algorithm |
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| 36 | === Watchdog timer === |
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| 37 | === Interrupt Controller === |
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| 38 | === Memory interface (SRAM/ROM) === |
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| 39 | === DMA controller === |
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| 40 | * Only usable for UART and RIF, can only DMA to small API RAM memory region |
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| 41 | === SIM card controller === |
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| 42 | * Connects to the SIM card socket in the phone |
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| 43 | === TSP controller (Time Serial Port) === |
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| 44 | * Controls the TSP, which controls the sequencing of all external peripherals like ABB, RF chip, RF PA, Antenna Switch |
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| 45 | === RTC clock === |
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| 46 | * A pretty standard realtime clock |
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| 47 | === ULPD (Ultra Low Power Device) === |
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| 48 | * Responsible for enabling the phone to go to lowest-possible power mode while IDLE, but still waking up at the right point to receive important data (like paging channel) from the BTS |
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| 49 | === I2C Master controller === |
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| 50 | * Typically connects to external peripherals like LCD (if any) |
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| 51 | 2 | laforge | |
| 52 | The controller has two oddities: |
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| 53 | 1 | laforge | * It assumes that the peripheral has an address byte. If your peripheral doesn't, you have to |
| 54 | write the first byte into the address register and not the FIFO |
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| 55 | * You cannot under-fill the FIFO, i.e. if you write 8 bytes into the 16byte deep fifo, the controller |
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| 56 | 2 | laforge | will transmit 16 bytes rather than 8. Therefore, always limit the FIFO depth to your write size! |
| 57 | 1 | laforge | More details about this can be seen at [wiki:CalypsoI2CFIFO] |
| 58 | 7 | laforge | === SPI Master controller === |
| 59 | * Connects to USP of ABB and possibly other external peripherals |
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| 60 | === TIMER1 / TIMER2 general purpose timers === |
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| 61 | 2 | laforge | The timer input clock is not mentioned in the data sheet. It seems to be 13MHz / 32, i.e. 406.25kHz |
| 62 | 7 | laforge | === PWL (PWM for Light) === |
| 63 | * connected to the screen/keypad backlight |
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| 64 | === PWT (PWM for Tones) === |
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| 65 | * connected to a buzzer for ringtone generation |
