Iota » History » Version 9
steve-m, 02/19/2016 10:48 PM
add link to bottom scan
| 1 | 1 | laforge | This is the Analog Baseband Chip TWL3025 |
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| 2 | 2 | laforge | |
| 3 | 8 | laforge | It's very similar to its predecessors, the TWL3014 and TWL3016 devices. |
| 4 | |||
| 5 | A data sheet for the TWL3014 is available from http://www.52rd.com/bbs/Detail_RD.BBS_8719_68_1_1.html |
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| 6 | but forum registration is required for download. |
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| 7 | |||
| 8 | 7 | laforge | It consists of various functions, including |
| 9 | * ADC and DAC for the GSM baseband signals |
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| 10 | * ADC and DAC for the Voice/Audio path |
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| 11 | * DAC for APC (Automatic Power Control) |
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| 12 | * DAC for AFC (Automatic Frequency Control) |
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| 13 | * Battery Charging Controller |
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| 14 | * LDO's (Linear Power Regulators) |
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| 15 | 1 | laforge | |
| 16 | 7 | laforge | The functions of the ABB are controlled by a register set. The register set |
| 17 | is available through both USP and BSP. |
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| 18 | |||
| 19 | == External Interfaces == |
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| 20 | === USP (uController Serial Port) === |
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| 21 | |||
| 22 | 4 | laforge | This is the SPI-like control interface between DBB and the TWL3025 (ABB). |
| 23 | 3 | laforge | |
| 24 | 1 | laforge | [[Image(Iota:twl3025_usp.png)]] |
| 25 | 2 | laforge | |
| 26 | 7 | laforge | === TSP (Timee Serial Port) === |
| 27 | 1 | laforge | |
| 28 | 9 | steve-m | It is connected to the TSP controller inside the [wiki:Hardware/Calypso] DBB. |
| 29 | 7 | laforge | |
| 30 | 2 | laforge | The CLK6.5 Signal makes things a bit more complicated than we would like. The sequence of events is something like: |
| 31 | 7 | laforge | * CLK_13M is applied continuously to TWL3025 |
| 32 | 2 | laforge | * nTEN is in default state of high (inactive) |
| 33 | * internal CLK6.5 is in default state low |
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| 34 | * nTEN is asserted low by TPU, some 0..65ns before CLK_13M rising edge |
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| 35 | * next CLK13M falling edge starts first CLK6.5 rising edge |
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| 36 | * every falling edge of CLK13M toggles CLK6.5 |
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| 37 | * TDR is sampled at every rising edge of CLK6.5 (including the first edge above) |
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| 38 | 1 | laforge | * 7 bits are transferred during seven rising edges of CLK6.5 |
| 39 | * TEN stays asserted for 1 CLK13M period after last bit is transferred |
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| 40 | * TEN needs to be released before next CLK13M rising edge to prevent another transfer |
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| 41 | 7 | laforge | |
| 42 | === BSP (Baseband Serial Port) === |
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| 43 | |||
| 44 | 1 | laforge | This synchronous serial port is connected to the RIF (Radio InterFace) of the Calypso DBB. |
| 45 | 9 | steve-m | |
| 46 | === Debug traces === |
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| 47 | |||
| 48 | The chip has very tiny debug traces on a small flex-pcb around the 4 sides of the chip. |
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| 49 | Which trace goes to which ball can be seen on this scan: http://www.steve-m.de/pictures/iota_bottom.jpg |
