IcE1usb » History » Version 9
laforge, 08/22/2020 07:14 AM
| 1 | 1 | tnt | h1. iCE40 E1 USB interface |
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| 3 | 7 | laforge | This page is the main entry point for the (completed!) "Software defined" E1 USB interface using the iCE40 FPGA at its core. |
| 4 | 1 | tnt | |
| 5 | h2. Architecture |
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| 7 | 2 | laforge | This approach tries to implement as much as possible inside an iCE40 FPGA |
| 8 | 1 | tnt | |
| 9 | Particularly, the iCE40 FPGA |
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| 10 | 2 | laforge | * contains the E1 PHY. There is no external LIU*, reducing the BOM cost significantly. Instead, the comparators of the FPGA are used. In practice, this has shown to work on short E1 links of a few meters. We'd expect some problems in terms of long-haul E1 links, but those are not really the target use case here. |
| 11 | 7 | laforge | * contains the E1 framer, including frame alignment, CRC4 verification/generation, ... |
| 12 | 2 | laforge | * contains a USB softcore (no external USB PHY needed) |
| 13 | * contains a PicoRISCV softcore to implement USB protocol handling and to connect the E1 softcore with the USB softcore |
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| 15 | So all-in-all, we can build a USB-E1 interface from little more than an iCE40 FPGA and an E1 line transformer! |
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| 17 | 4 | laforge | !{width:50%}ice40-e1.jpg! |
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| 19 | 1 | tnt | h2. Current stack |
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| 21 | 9 | laforge | * The hardware is currently not documented, only few prototypes exists and have been half hand-wired. They are currently based off iCEBreaker and iCEBreaker-bitsy iCE40 dev boards. ( https://github.com/icebreaker-fpga/icebreaker ) as well as iCEpick by @tnt |
| 22 | 1 | tnt | * The gateware is temporarily hosted in the 'e1' branch of this repo : https://github.com/smunaut/ice40-playground/tree/e1/projects/riscv_usb |
| 23 | * The embedded software is in the same repository as above, in the 'fw' sub-directory : https://github.com/smunaut/ice40-playground/tree/e1/projects/riscv_usb/fw |
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| 24 | 2 | laforge | * The userspace daemon that handles the USB communication is hosted at: https://git.osmocom.org/osmo-e1d |
| 25 | 5 | laforge | * The support for this daemon interface to the rest of the cellular stack is merged in mainline [[libosmo-abis:]]. Make sure you build it with @--enable-e1d@, though. |
| 26 | 1 | tnt | |
| 27 | h2. Presentations |
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| 29 | * Talk from OsmoCon 2018 about the Software Defined E1 project as a whole : attachment:osmocon_2018_e1.pdf |
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| 30 | * Talk from OsmoDevCon 2019 about the iCE40 based solution specifically: attachment:osmodevcon_2019_e1.pdf |
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| 31 | 7 | laforge | * "video recording of the iC40 based approach / OsmoDevCon 2019":https://media.ccc.de/v/osmodevcon2019-97-software-defined-e1 |
| 32 | 1 | tnt | |
| 33 | h2. Status |
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| 35 | 7 | laforge | h3. Hardware |
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| 37 | * Several hand-wired pre-production prototypes based on iCEbreaker and iCEbreaker-bitsy or iCEpick have been assembled and used successfully in 2019 and early 2020 |
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| 38 | * A fully integrated single-board design with two E1 lines and a GPS-DO for E1 clock stability has been created by @tnt in August 2020; prototype boards exist, and we expect a first production run is imminent. |
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| 41 | h3. Software |
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| 43 | The full stack from gateware through firmware and host software has been tested and used in a variety of scenarios. |
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| 45 | * gateware for the FPGA and firmware for the RISC-V softcore is available from the @e1@ branch of @ice40-playground.git@, see https://github.com/smunaut/ice40-playground/tree/e1 |
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| 46 | 1 | tnt | * The host software/driver is part of [[osmo-e1d:]], see the proejct page for related details. [[libosmo-abis:]] has been extended with [[osmo-e1d:]] support. |
| 47 | 8 | laforge | |
| 48 | h2. Credits |
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| 49 | |||
| 50 | The development of FPGA softcores, firmware, PCB schematics, PCB layout and osmo-e1d was done by Sylvain Munat (@tnt). |
