osmo-sdr/firmware/include/osdr_fpga.h @ master
1 | dd77bb2e | Harald Welte | #ifndef _OSDR_FGPA_H
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2 | #define _OSDR_FGPA_H
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3 | |||
4 | 5fb405d4 | Harald Welte | enum osdr_fpga_reg { |
5 | OSDR_FPGA_REG_ID = 0, |
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6 | OSDR_FPGA_REG_PWM1 = 1, |
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7 | OSDR_FPGA_REG_PWM2 = 2, |
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8 | OSDR_FPGA_REG_ADC_TIMING = 3, |
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9 | OSDR_FPGA_REG_DUMMY = 4, |
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10 | OSDR_FPGA_REG_ADC_VAL = 5, |
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11 | 399d4147 | Christian Daniel | OSDR_FPGA_REG_DECIMATION = 6, |
12 | OSDR_FPGA_REG_IQ_OFS = 7, |
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13 | OSDR_FPGA_REG_IQ_GAIN = 8, |
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14 | OSDR_FPGA_REG_IQ_SWAP = 9, |
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15 | 5fb405d4 | Harald Welte | };
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16 | |||
17 | dd77bb2e | Harald Welte | void osdr_fpga_power(int on); |
18 | 5fb405d4 | Harald Welte | void osdr_fpga_init(uint32_t masterClock); |
19 | uint32_t osdr_fpga_reg_read(uint8_t reg); |
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20 | void osdr_fpga_reg_write(uint8_t reg, uint32_t val); |
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21 | 399d4147 | Christian Daniel | void osdr_fpga_set_decimation(uint8_t val); |
22 | void osdr_fpga_set_iq_swap(uint8_t val); |
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23 | void osdr_fpga_set_iq_gain(uint16_t igain, uint16_t qgain); |
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24 | void osdr_fpga_set_iq_ofs(int16_t iofs, int16_t qofs); |
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25 | dd77bb2e | Harald Welte | |
26 | #endif
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