1 |
83340d0b
|
Christian Daniel
|
-----------------------------------------------------------------------------------
|
2 |
|
|
-- Filename : mt_synctools.vhd
|
3 |
|
|
-- Project : maintech IP-Core toolbox
|
4 |
|
|
-- Purpose : Basic tools for clock-domain-crossings
|
5 |
|
|
--
|
6 |
|
|
-----------------------------------------------------------------------------------
|
7 |
|
|
|
8 |
|
|
-----------------------------------------------------------------------------------
|
9 |
|
|
-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
|
10 |
|
|
-- written by Matthias Kleffel --
|
11 |
|
|
-- --
|
12 |
|
|
-- This program is free software; you can redistribute it and/or modify --
|
13 |
|
|
-- it under the terms of the GNU General Public License as published by --
|
14 |
|
|
-- the Free Software Foundation as version 3 of the License, or --
|
15 |
|
|
-- --
|
16 |
|
|
-- This program is distributed in the hope that it will be useful, --
|
17 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
|
18 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
|
19 |
|
|
-- GNU General Public License V3 for more details. --
|
20 |
|
|
-- --
|
21 |
|
|
-- You should have received a copy of the GNU General Public License --
|
22 |
|
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
|
23 |
|
|
-----------------------------------------------------------------------------------
|
24 |
|
|
|
25 |
|
|
|
26 |
|
|
------------------------------------------------------------------------------
|
27 |
|
|
-- mt_sync_dualff (dual flip-flop synchronizer) -------------------------------
|
28 |
|
|
-------------------------------------------------------------------------------
|
29 |
|
|
|
30 |
|
|
library ieee;
|
31 |
|
|
use ieee.std_logic_1164.all;
|
32 |
|
|
library work;
|
33 |
|
|
use work.mt_toolbox.all;
|
34 |
|
|
|
35 |
|
|
entity mt_sync_dualff is
|
36 |
|
|
port(
|
37 |
|
|
-- input
|
38 |
|
|
i_data : in std_logic;
|
39 |
|
|
|
40 |
|
|
-- output
|
41 |
|
|
o_clk : in std_logic;
|
42 |
|
|
o_data : out std_logic
|
43 |
|
|
);
|
44 |
|
|
end mt_sync_dualff;
|
45 |
|
|
|
46 |
|
|
architecture rtl of mt_sync_dualff is
|
47 |
|
|
-- signals
|
48 |
|
|
signal sreg : std_logic := '0';
|
49 |
|
|
signal oreg : std_logic := '0';
|
50 |
|
|
|
51 |
|
|
-- no SRL16s here...
|
52 |
|
|
attribute shreg_extract of sreg : signal is "no";
|
53 |
|
|
attribute shreg_extract of oreg : signal is "no";
|
54 |
|
|
|
55 |
|
|
begin
|
56 |
|
|
process(o_clk)
|
57 |
|
|
begin
|
58 |
|
|
if rising_edge(o_clk) then
|
59 |
|
|
sreg <= i_data;
|
60 |
|
|
oreg <= sreg;
|
61 |
|
|
end if;
|
62 |
|
|
end process;
|
63 |
|
|
o_data <= oreg;
|
64 |
|
|
end rtl;
|
65 |
|
|
|
66 |
|
|
|
67 |
|
|
-------------------------------------------------------------------------------
|
68 |
|
|
-- mt_sync_feedback (feedback synchronizer) -----------------------------------
|
69 |
|
|
-------------------------------------------------------------------------------
|
70 |
|
|
|
71 |
|
|
library ieee;
|
72 |
|
|
use ieee.std_logic_1164.all;
|
73 |
|
|
library work;
|
74 |
|
|
use work.mt_toolbox.all;
|
75 |
|
|
|
76 |
|
|
entity mt_sync_feedback is
|
77 |
|
|
port(
|
78 |
|
|
-- input
|
79 |
|
|
i_clk : in std_logic;
|
80 |
|
|
i_data : in std_logic;
|
81 |
|
|
|
82 |
|
|
-- output
|
83 |
|
|
o_clk : in std_logic;
|
84 |
|
|
o_data : out std_logic
|
85 |
|
|
);
|
86 |
|
|
end mt_sync_feedback;
|
87 |
|
|
|
88 |
|
|
architecture rtl of mt_sync_feedback is
|
89 |
|
|
|
90 |
|
|
signal flip_i : std_logic := '0';
|
91 |
|
|
signal flip_s1 : std_logic := '0';
|
92 |
|
|
signal flip_s2 : std_logic := '0';
|
93 |
|
|
signal flip_s3 : std_logic := '0';
|
94 |
|
|
signal oreg : std_logic := '0';
|
95 |
|
|
|
96 |
|
|
attribute syn_keep of flip_i : signal is true;
|
97 |
|
|
attribute syn_keep of flip_s1 : signal is true;
|
98 |
|
|
attribute syn_keep of flip_s2 : signal is true;
|
99 |
|
|
attribute syn_keep of flip_s3 : signal is true;
|
100 |
|
|
attribute syn_keep of oreg : signal is true;
|
101 |
|
|
|
102 |
|
|
begin
|
103 |
|
|
|
104 |
|
|
process(i_clk)
|
105 |
|
|
begin
|
106 |
|
|
if rising_edge(i_clk) then
|
107 |
|
|
-- update flip-bit on request
|
108 |
|
|
if i_data='1' then
|
109 |
|
|
flip_i <= not flip_i;
|
110 |
|
|
end if;
|
111 |
|
|
|
112 |
|
|
-- debug check
|
113 |
|
|
assert not (i_data='1' and flip_s1/=flip_i)
|
114 |
|
|
report "mt_sync_feedback: pulses too close, failed to synchronize"
|
115 |
|
|
severity failure;
|
116 |
|
|
end if;
|
117 |
|
|
end process;
|
118 |
|
|
|
119 |
|
|
process(o_clk)
|
120 |
|
|
begin
|
121 |
|
|
if rising_edge(o_clk) then
|
122 |
|
|
-- synchronize flip-bit
|
123 |
|
|
flip_s1 <= flip_i;
|
124 |
|
|
flip_s2 <= flip_s1;
|
125 |
|
|
flip_s3 <= flip_s2;
|
126 |
|
|
|
127 |
|
|
-- create output-request
|
128 |
|
|
oreg <= flip_s3 xor flip_s2;
|
129 |
|
|
end if;
|
130 |
|
|
end process;
|
131 |
|
|
|
132 |
|
|
-- set output
|
133 |
|
|
o_data <= oreg;
|
134 |
|
|
|
135 |
|
|
end rtl;
|