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-----------------------------------------------------------------------------------
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-- Filename : mt_synctools.vhd
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-- Project : maintech IP-Core toolbox
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-- Purpose : Basic tools for clock-domain-crossings
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--
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-----------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
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-- Copyright (C) 2012 maintech GmbH, Otto-Hahn-Str. 15, 97204 Hoechberg, Germany --
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-- written by Matthias Kleffel --
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-- --
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-- This program is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published by --
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-- the Free Software Foundation as version 3 of the License, or --
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-- --
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-- This program is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License V3 for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-----------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- mt_sync_dualff (dual flip-flop synchronizer) -------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.mt_toolbox.all;
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entity mt_sync_dualff is
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port(
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-- input
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i_data : in std_logic;
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-- output
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o_clk : in std_logic;
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o_data : out std_logic
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);
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end mt_sync_dualff;
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architecture rtl of mt_sync_dualff is
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-- signals
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signal sreg : std_logic := '0';
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signal oreg : std_logic := '0';
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-- no SRL16s here...
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attribute shreg_extract of sreg : signal is "no";
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attribute shreg_extract of oreg : signal is "no";
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begin
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process(o_clk)
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begin
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if rising_edge(o_clk) then
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sreg <= i_data;
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oreg <= sreg;
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end if;
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end process;
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o_data <= oreg;
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end rtl;
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-------------------------------------------------------------------------------
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-- mt_sync_feedback (feedback synchronizer) -----------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.mt_toolbox.all;
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entity mt_sync_feedback is
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port(
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-- input
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i_clk : in std_logic;
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i_data : in std_logic;
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-- output
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o_clk : in std_logic;
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o_data : out std_logic
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);
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end mt_sync_feedback;
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architecture rtl of mt_sync_feedback is
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signal flip_i : std_logic := '0';
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signal flip_s1 : std_logic := '0';
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signal flip_s2 : std_logic := '0';
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signal flip_s3 : std_logic := '0';
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signal oreg : std_logic := '0';
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attribute syn_keep of flip_i : signal is true;
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attribute syn_keep of flip_s1 : signal is true;
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attribute syn_keep of flip_s2 : signal is true;
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attribute syn_keep of flip_s3 : signal is true;
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attribute syn_keep of oreg : signal is true;
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begin
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process(i_clk)
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begin
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if rising_edge(i_clk) then
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-- update flip-bit on request
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if i_data='1' then
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flip_i <= not flip_i;
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end if;
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-- debug check
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assert not (i_data='1' and flip_s1/=flip_i)
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report "mt_sync_feedback: pulses too close, failed to synchronize"
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severity failure;
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end if;
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end process;
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process(o_clk)
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begin
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if rising_edge(o_clk) then
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-- synchronize flip-bit
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flip_s1 <= flip_i;
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flip_s2 <= flip_s1;
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flip_s3 <= flip_s2;
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-- create output-request
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oreg <= flip_s3 xor flip_s2;
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end if;
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end process;
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-- set output
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o_data <= oreg;
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end rtl;
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