XMU 02 » History » Version 1
laforge, 11/07/2020 08:36 AM
| 1 | 1 | laforge | h1. XMU 02 |
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| 3 | The XMU 02 seems to be some kind of CPRI front-haulmultiplexor. It appears to be used in situations where a (small number of) high-bitrate CPRI links from the DU is to be de-multiplexed to multiple more lower-bitrated CPRI links towards the RU. |
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| 5 | It appears to be controlled via some RS485 based control channel. There are three MAX3485 transcevers for each of the three RJ45 connectors on the front (A1, A2, A3). |
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| 7 | h2. Internal structure |
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| 9 | h3. FPGA |
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| 11 | Internally, it appears to be one large (44x44mm, >= 42x42 ball BGA) part, probably a FPGA, connected to the 14 SFP+ slots for CPRI. |
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| 13 | h3. SoC |
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| 15 | There's a control SoC ("Ericsson ROP 101 1190/2") with FLASH + RAM |
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| 16 | * Intel/Micron/Numonyx "RC48F4400P0VB0E":https://www.digchip.com/datasheets/download_datasheet.php?id=7512107&part-number=RC48F4400P0VB0E 512Mbit/64MByte NOR flash |
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| 17 | * ISSI "IS42S32800D-7TLI":http://www.issi.com/WW/pdf/42-45S32800D.pdf 256MBit/32MByte SDRAM |
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| 19 | h3. Clocking |
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| 21 | There are three clock sections, |
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| 22 | * Two seemingly identical sections comprised of |
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| 23 | ** "ERC3105E 491.52" Part (491.52 MHz?) |
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| 24 | ** "AD9510 Clock Distribution/PLL IC":https://www.analog.com/media/en/technical-documentation/data-sheets/AD9510.pdf |
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| 25 | ** "MAX8869 LDO":https://www.maximintegrated.com/en/products/power/linear-regulators/MAX8869.html |
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| 26 | * One section consisting of |
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| 27 | ** VDSCLD 63.897 (63.897 MHz?) |
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| 28 | ** "AD9510 Clock Distribution/PLL IC":https://www.analog.com/media/en/technical-documentation/data-sheets/AD9510.pdf |
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| 29 | ** "MAX8869 LDO":https://www.maximintegrated.com/en/products/power/linear-regulators/MAX8869.html |
