Dimetra EBTS Site Controller » History » Version 12
laforge, 02/21/2016 11:29 AM
1 | 9 | laforge | {{>toc}} |
---|---|---|---|
2 | 1 | laforge | |
3 | 9 | laforge | h1. Integrated Site Controller (CLN1480A) |
4 | |||
5 | |||
6 | 1 | laforge | This is a unit that interfaces up to 8 Base Radios with the core network of the Dimetra TETRA network (SwMI). |
7 | |||
8 | 11 | laforge | Hardware-wise, it is a PowerPC based system, looking very much like an old-fashioned PC mainboard with both ISA and PCI slots. |
9 | 1 | laforge | |
10 | 11 | laforge | The mainboard houses the PowerPC CPU and it has slots for RAM. |
11 | 1 | laforge | |
12 | There are some extension cards plugged into the system: |
||
13 | |||
14 | 9 | laforge | * Clock generation card (ISA, full length). |
15 | ** has an integrated GPS receiver, to which you attach a GPS antenna |
||
16 | ** generates the reference 5MHz clock distributed over Coaxial cable to the Base Radios |
||
17 | * Ethernet Card using DEC tulip chipset (PCI) |
||
18 | ** This card is what talks to the Base Radios (BR) via 10-Base-2 |
||
19 | * Unknown card with RJ-45 jack (REDUND) on the back. Might be E1 |
||
20 | 1 | laforge | |
21 | There are further inputs and outputs on the system: |
||
22 | |||
23 | 9 | laforge | **** A DB-15 jack for X.21 synchronous serial backhaul (2048Mbps) |
24 | **** FIXME |
||
25 | **** A RS-232 serial port for local configuration |
||
26 | 1 | laforge | |
27 | 9 | laforge | |
28 | 12 | laforge | h2. Serial Console |
29 | 10 | laforge | |
30 | h3. Boot Log |
||
31 | |||
32 | 9 | laforge | <pre> |
33 | 8 | laforge | Copyright Motorola Inc. 1988 - 1996, All Rights Reserved |
34 | |||
35 | 1 | laforge | ACG Debugger/Diagnostics Release Version 1.0 - 06/24/96 |
36 | 8 | laforge | COLD Start |
37 | |||
38 | Local Memory Found =02000000 (&33554432) |
||
39 | |||
40 | MPU Clock Speed =100Mhz |
||
41 | |||
42 | BUS Clock Speed =67Mhz |
||
43 | |||
44 | Keyboard not connected |
||
45 | |||
46 | Initializing System Memory (DRAM)... |
||
47 | |||
48 | System Memory: 32MB, Parity NOT Enabled (Non-Parity-Memory Detected) |
||
49 | L2Cache: NONE, Parity NOT Enabled |
||
50 | |||
51 | |||
52 | 9 | laforge | [[SelfTest]]/Boots about to Begin... Press <BREAK> at anytime to Abort ALL |
53 | 8 | laforge | |
54 | ROMBoot about to Begin... Press <ESC> to Bypass, <SPC> to Continue |
||
55 | _ |
||
56 | DEC DC21140 (rev 0x2000022) at 0x80810000, irq 9, hwaddr 08:00:3e:c4:d6:9d |
||
57 | AMCC Motorola SEP/STP at 0x80840000, irq 14 |
||
58 | SRI site reference/watchdog at 0x80000200, board rev. 2 |
||
59 | Memory: 16535k/32768k available (76k kernel, 0k reserved) |
||
60 | |||
61 | Access Controller Gateway |
||
62 | Firmware Rev R02.03.02 (PowerPC) |
||
63 | Copyright (c) 1993-1996 |
||
64 | Motorola, Inc. |
||
65 | |||
66 | Unauthorized Access Prohibited |
||
67 | |||
68 | Current status: |
||
69 | 1 | laforge | |
70 | Active/Standby Status: UNKNOWN |
||
71 | MAC Address: 08:00:3e:c4:d6:9d |
||
72 | |||
73 | 8 | laforge | To enter configuration mode, hit any key within 10 seconds: |
74 | Waiting for ACTIVE/STANDBY status determination... |
||
75 | Booting from T1 interface (hit any key to abort). |
||
76 | |||
77 | |||
78 | ERROR - T1 initialization failed: Stabilization error |
||
79 | |||
80 | |||
81 | |||
82 | ERROR - T1 initialization failed: Stabilization error |
||
83 | |||
84 | |||
85 | |||
86 | ERROR - T1 initialization failed: Stabilization error |
||
87 | 9 | laforge | </pre> |
88 | 8 | laforge | |
89 | 9 | laforge | |
90 | h3. Menu |
||
91 | |||
92 | <pre> |
||
93 | 1 | laforge | Enter "help" for a list of commands |
94 | 8 | laforge | ACG> help |
95 | 1 | laforge | |
96 | Available commands: |
||
97 | dir - Show file directory |
||
98 | 8 | laforge | exit - Exit configuration mode |
99 | go - Execute application code |
||
100 | 1 | laforge | help - Print this info |
101 | inport - Dump input from a serial port |
||
102 | load - Load file into memory via ethernet |
||
103 | 8 | laforge | loadall - Load all files into memory via ethernet |
104 | 1 | laforge | nvr - Dump NVRAM |
105 | outport - Send output to a serial port |
||
106 | passwd - Change operator password |
||
107 | 8 | laforge | reset - Reboot this processor |
108 | sload - Load S-records from serial port |
||
109 | status - Print configuration parameters |
||
110 | ver - Print firmware version |
||
111 | ACG> |
||
112 | 9 | laforge | </pre> |
113 | 1 | laforge | |
114 | 9 | laforge | |
115 | 10 | laforge | h2. Pictures |
116 | 1 | laforge | |
117 | 10 | laforge | h3. Site Controller top view (lid removed) |
118 | 1 | laforge | |
119 | 10 | laforge | !{width:60%}tetra_site_controller_open.jpg! |
120 | |||
121 | |||
122 | 9 | laforge | h3. PCI Card with lots of Lucent chips |
123 | 1 | laforge | |
124 | 10 | laforge | !{width:60%}tetra_site_controller_lucent_pcb_top.jpg! |
125 | !{width:60%}tetra_site_controller_lucent_pcb_bottom.jpg! |
||
126 | 1 | laforge | |
127 | |||
128 | 9 | laforge | h3. PCI Ethernet card (10-Base-2) |
129 | |||
130 | 10 | laforge | !{width:60%}tetra_site_controller_ethernet_pcb_top.jpg! |
131 | 7 | laforge | |
132 | 9 | laforge | |
133 | h3. Clock card |
||
134 | |||
135 | 10 | laforge | !{width:60%}tetra_site_controller_clock_pcb_top.jpg! |
136 | !{width:60%}tetra_site_controller_clock_pcb_bottom.jpg! |