Dimetra EBTS Site Controller » History » Version 9
laforge, 02/19/2016 10:52 PM
1 | 9 | laforge | {{>toc}} |
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2 | 1 | laforge | |
3 | 9 | laforge | h1. Integrated Site Controller (CLN1480A) |
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6 | 1 | laforge | This is a unit that interfaces up to 8 Base Radios with the core network of the Dimetra TETRA network (SwMI). |
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8 | 9 | laforge | Hardware-wise, it is a [[PowerPC]] based system, looking very much like an old-fashioned PC mainboard with both ISA and PCI slots. |
9 | 1 | laforge | |
10 | 9 | laforge | The mainboard houses the [[PowerPC]] CPU and it has slots for RAM. |
11 | 1 | laforge | |
12 | There are some extension cards plugged into the system: |
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13 | |||
14 | 9 | laforge | * Clock generation card (ISA, full length). |
15 | ** has an integrated GPS receiver, to which you attach a GPS antenna |
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16 | ** generates the reference 5MHz clock distributed over Coaxial cable to the Base Radios |
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17 | * Ethernet Card using DEC tulip chipset (PCI) |
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18 | ** This card is what talks to the Base Radios (BR) via 10-Base-2 |
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19 | * Unknown card with RJ-45 jack (REDUND) on the back. Might be E1 |
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20 | 1 | laforge | |
21 | There are further inputs and outputs on the system: |
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23 | 9 | laforge | **** A DB-15 jack for X.21 synchronous serial backhaul (2048Mbps) |
24 | **** FIXME |
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25 | **** A RS-232 serial port for local configuration |
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26 | 1 | laforge | |
27 | 9 | laforge | |
28 | h2. Serial Console == |
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29 | Boot Log === |
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30 | <pre> |
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31 | 8 | laforge | Copyright Motorola Inc. 1988 - 1996, All Rights Reserved |
32 | |||
33 | 1 | laforge | ACG Debugger/Diagnostics Release Version 1.0 - 06/24/96 |
34 | 8 | laforge | COLD Start |
35 | |||
36 | Local Memory Found =02000000 (&33554432) |
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37 | |||
38 | MPU Clock Speed =100Mhz |
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39 | |||
40 | BUS Clock Speed =67Mhz |
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41 | |||
42 | Keyboard not connected |
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43 | |||
44 | Initializing System Memory (DRAM)... |
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45 | |||
46 | System Memory: 32MB, Parity NOT Enabled (Non-Parity-Memory Detected) |
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47 | L2Cache: NONE, Parity NOT Enabled |
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48 | |||
49 | |||
50 | 9 | laforge | [[SelfTest]]/Boots about to Begin... Press <BREAK> at anytime to Abort ALL |
51 | 8 | laforge | |
52 | ROMBoot about to Begin... Press <ESC> to Bypass, <SPC> to Continue |
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53 | _ |
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54 | DEC DC21140 (rev 0x2000022) at 0x80810000, irq 9, hwaddr 08:00:3e:c4:d6:9d |
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55 | AMCC Motorola SEP/STP at 0x80840000, irq 14 |
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56 | SRI site reference/watchdog at 0x80000200, board rev. 2 |
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57 | Memory: 16535k/32768k available (76k kernel, 0k reserved) |
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58 | |||
59 | Access Controller Gateway |
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60 | Firmware Rev R02.03.02 (PowerPC) |
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61 | Copyright (c) 1993-1996 |
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62 | Motorola, Inc. |
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63 | |||
64 | Unauthorized Access Prohibited |
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65 | |||
66 | Current status: |
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67 | 1 | laforge | |
68 | Active/Standby Status: UNKNOWN |
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69 | MAC Address: 08:00:3e:c4:d6:9d |
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71 | 8 | laforge | To enter configuration mode, hit any key within 10 seconds: |
72 | Waiting for ACTIVE/STANDBY status determination... |
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73 | Booting from T1 interface (hit any key to abort). |
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74 | |||
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76 | ERROR - T1 initialization failed: Stabilization error |
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80 | ERROR - T1 initialization failed: Stabilization error |
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84 | ERROR - T1 initialization failed: Stabilization error |
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85 | 9 | laforge | </pre> |
86 | 8 | laforge | |
87 | 9 | laforge | |
88 | h3. Menu |
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89 | |||
90 | <pre> |
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91 | 1 | laforge | Enter "help" for a list of commands |
92 | 8 | laforge | ACG> help |
93 | 1 | laforge | |
94 | Available commands: |
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95 | dir - Show file directory |
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96 | 8 | laforge | exit - Exit configuration mode |
97 | go - Execute application code |
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98 | 1 | laforge | help - Print this info |
99 | inport - Dump input from a serial port |
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100 | load - Load file into memory via ethernet |
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101 | 8 | laforge | loadall - Load all files into memory via ethernet |
102 | 1 | laforge | nvr - Dump NVRAM |
103 | outport - Send output to a serial port |
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104 | passwd - Change operator password |
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105 | 8 | laforge | reset - Reboot this processor |
106 | sload - Load S-records from serial port |
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107 | status - Print configuration parameters |
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108 | ver - Print firmware version |
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109 | ACG> |
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110 | 9 | laforge | </pre> |
111 | 8 | laforge | |
112 | 9 | laforge | |
113 | h2. Images == |
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114 | Site Controller top view (lid removed) === |
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115 | 8 | laforge | [[Image(tetra_site_controller_open.jpg, 66%)]] |
116 | 1 | laforge | |
117 | 9 | laforge | |
118 | h3. PCI Card with lots of Lucent chips |
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119 | |||
120 | 4 | laforge | [[Image(tetra_site_controller_lucent_pcb_top.jpg, 50%)]] |
121 | 5 | laforge | [[Image(tetra_site_controller_lucent_pcb_bottom.jpg, 50%)]] |
122 | |||
123 | 9 | laforge | |
124 | h3. PCI Ethernet card (10-Base-2) |
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125 | |||
126 | 7 | laforge | [[Image(tetra_site_controller_ethernet_pcb_top.jpg, 50%)]] |
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128 | 9 | laforge | |
129 | h3. Clock card |
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130 | |||
131 | 1 | laforge | [[Image(tetra_site_controller_clock_pcb_top.jpg, 50%)]] |
132 | [[Image(tetra_site_controller_clock_pcb_bottom.jpg, 50%)]] |